Date: Sun, 7 Jul 2024 18:05:14 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V SoC drivers for v6.11 --===============7830153249983487876== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="xGmgvF5AKXzK9lgj" Content-Disposition: inline --xGmgvF5AKXzK9lgj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Please pull the addition of a new cache driver. There's a wee maintainers update in here too, I put the series on this branch as one patch is cache related and I have no soc driver patches. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.11 for you to fetch changes up to 3d41249c1dee0fa22ebd8d27aa0a280edf943a0e: MAINTAINERS: add microchip soc binding directory to microchip soc driver entry (2024-06-27 17:33:06 +0100) ---------------------------------------------------------------- RISC-V cache drivers for v6.11 StarFive: A new driver for the cache controller on the jh8100, which didn't implement Zicbom and thus needs an implementation of non-standard cache management operations. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (2): MAINTAINERS: add cache binding directory to cache driver entry MAINTAINERS: add microchip soc binding directory to microchip soc driver entry Joshua Yeong (2): dt-bindings: cache: Add docs for StarFive Starlink cache controller cache: Add StarFive StarLink cache management .../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++++ MAINTAINERS | 2 + drivers/cache/Kconfig | 9 ++ drivers/cache/Makefile | 5 +- drivers/cache/starfive_starlink_cache.c | 130 +++++++++++++++++++++ 5 files changed, 210 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml create mode 100644 drivers/cache/starfive_starlink_cache.c --xGmgvF5AKXzK9lgj Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorKygAKCRB4tDGHoIJi 0trFAP4wCehxgeMtIUbFBhtUjWWvb4WPWehGCmpjuWYSWwhcLgEA4bHZd2Dxro1s Sw96HJ0lkKIj0o8MZDfAepbYm94eIAQ= =czaE -----END PGP SIGNATURE----- --xGmgvF5AKXzK9lgj-- --===============7830153249983487876== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============7830153249983487876==-- . Date: Sun, 7 Jul 2024 18:11:05 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V SoC drivers for v6.11 --===============7776583627235315919== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Ri8/7/7BqJ3GSS4x" Content-Disposition: inline --Ri8/7/7BqJ3GSS4x Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Single commit here, I discussed with Palmer about taking these defconfig patches for board support etc via the soc tree, so we're gonna try that. For now, only one commit here. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-config-for-v6.11 for you to fetch changes up to d8a7d89abb091fe4c1744241c7a40dbad570fd9e: riscv: defconfig: Enable StarFive JH7110 drivers (2024-06-12 23:16:55 +0100) ---------------------------------------------------------------- RISC-V config update for v6.11 StarFive: Enable most of the options needed for the jh7100 based boards to be properly testable with defconfig. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Hal Feng (1): riscv: defconfig: Enable StarFive JH7110 drivers arch/riscv/configs/defconfig | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) --Ri8/7/7BqJ3GSS4x Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorMKQAKCRB4tDGHoIJi 0m9rAQDSRDFBr9wyNQGIbFthyjF08NwDYmzot4/4UrCfkz2nQgEAhEV9ToaAWJCy 25375xQXWfJhGM3xwwqVd4m61HBUfg4= =nYmR -----END PGP SIGNATURE----- --Ri8/7/7BqJ3GSS4x-- --===============7776583627235315919== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============7776583627235315919==-- . Date: Sun, 7 Jul 2024 18:20:14 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V SoC drivers for v6.11 --===============5575354421330108465== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="LQbIIb9DOF9VsMd1" Content-Disposition: inline --LQbIIb9DOF9VsMd1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Please pull a handful of changes to the Auto Update driver. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-firmware-for-v6.11 for you to fetch changes up to d930eb4fdfee32e0a3e9a5c9c2af8d65857ac4de: firmware: microchip: use scope-based cleanup where possible (2024-06-05 19:36:17 +0100) ---------------------------------------------------------------- RISC-V firmware drivers for v6.11 Microchip: Support for writing "bitstream info" to the flash using the auto-update driver. At this point the "bitstream info" is a glorified dtbo wrapper, but there's plans to add more info there in the future. Additionally, rework some allocations in the driver and use scope-based cleanup on them. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (3): firmware: microchip: support writing bitstream info to flash firmware: microchip: move buffer allocation into mpfs_auto_update_set_image_address() firmware: microchip: use scope-based cleanup where possible drivers/firmware/microchip/mpfs-auto-update.c | 136 +++++++++++++------------- 1 file changed, 67 insertions(+), 69 deletions(-) --LQbIIb9DOF9VsMd1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorOTgAKCRB4tDGHoIJi 0tU8APsG402BUKYU4sG18yezDQxes03LamExL1FEzqwjP2oZWAD9G5L3ffXIX15a Wegp/0q9sPUgmCjM4DKjGhY+sSRHUAM= =JcM2 -----END PGP SIGNATURE----- --LQbIIb9DOF9VsMd1-- --===============5575354421330108465== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============5575354421330108465==-- . Date: Sun, 7 Jul 2024 18:23:45 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V firmware drivers for v6.11 --===============0060219649721656974== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="dzNMppHeLU5ud5xK" Content-Disposition: inline --dzNMppHeLU5ud5xK Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Attempt 2 with a fixed $subject. I blame being sick for missing that.. Please pull a handful of changes to the Auto Update driver. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-firmware-for-v6.11 for you to fetch changes up to d930eb4fdfee32e0a3e9a5c9c2af8d65857ac4de: firmware: microchip: use scope-based cleanup where possible (2024-06-05 19:36:17 +0100) ---------------------------------------------------------------- RISC-V firmware drivers for v6.11 Microchip: Support for writing "bitstream info" to the flash using the auto-update driver. At this point the "bitstream info" is a glorified dtbo wrapper, but there's plans to add more info there in the future. Additionally, rework some allocations in the driver and use scope-based cleanup on them. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (3): firmware: microchip: support writing bitstream info to flash firmware: microchip: move buffer allocation into mpfs_auto_update_set_image_address() firmware: microchip: use scope-based cleanup where possible drivers/firmware/microchip/mpfs-auto-update.c | 136 +++++++++++++------------- 1 file changed, 67 insertions(+), 69 deletions(-) --dzNMppHeLU5ud5xK Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorPIQAKCRB4tDGHoIJi 0sANAP9bG1K7y/ld1oIlIANO1X2CSkjouvdLAZI4cGnCvgF5NgD9HFkF+Ehehl9b 9cDjuyr0WS+aDzXGGqwTqrGeDuaQrQE= =XXpr -----END PGP SIGNATURE----- --dzNMppHeLU5ud5xK-- --===============0060219649721656974== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============0060219649721656974==-- . Date: Sun, 7 Jul 2024 18:27:42 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V cache drivers for v6.11 --===============4772597711155964699== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="KT7UcFXDAuTnOBPW" Content-Disposition: inline --KT7UcFXDAuTnOBPW Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Another attempt 2 with a fixed $subject. Please pull the addition of a new cache driver. There's a wee maintainers update in here too, I put the series on this branch as one patch is cache related and I have no soc driver patches. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.11 for you to fetch changes up to 3d41249c1dee0fa22ebd8d27aa0a280edf943a0e: MAINTAINERS: add microchip soc binding directory to microchip soc driver entry (2024-06-27 17:33:06 +0100) ---------------------------------------------------------------- RISC-V cache drivers for v6.11 StarFive: A new driver for the cache controller on the jh8100, which didn't implement Zicbom and thus needs an implementation of non-standard cache management operations. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (2): MAINTAINERS: add cache binding directory to cache driver entry MAINTAINERS: add microchip soc binding directory to microchip soc driver entry Joshua Yeong (2): dt-bindings: cache: Add docs for StarFive Starlink cache controller cache: Add StarFive StarLink cache management .../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++++ MAINTAINERS | 2 + drivers/cache/Kconfig | 9 ++ drivers/cache/Makefile | 5 +- drivers/cache/starfive_starlink_cache.c | 130 +++++++++++++++++++++ 5 files changed, 210 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml create mode 100644 drivers/cache/starfive_starlink_cache.c --KT7UcFXDAuTnOBPW Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorQDgAKCRB4tDGHoIJi 0iTyAQC6E5jYycKU+W7zDH3Kc7JAcmcrw06+Um3pNJEHi3T+/gEA6V2PtoEkU1Al cYhBwKBi41JgCH/GmSmCHGT8I8TXkwQ= =I61w -----END PGP SIGNATURE----- --KT7UcFXDAuTnOBPW-- --===============4772597711155964699== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4772597711155964699==-- . Date: Sun, 7 Jul 2024 18:28:38 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com Subject: [GIT PULL] RISC-V defconfig for v6.11 --===============1361212987095751414== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="8e9vZ7cZueqeuYTs" Content-Disposition: inline --8e9vZ7cZueqeuYTs Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, The 3rd attempt 2 with a fixed $subject. Single commit here, I discussed with Palmer about taking these defconfig patches for board support etc via the soc tree, so we're gonna try that. For now, only one commit here. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-config-for-v6.11 for you to fetch changes up to d8a7d89abb091fe4c1744241c7a40dbad570fd9e: riscv: defconfig: Enable StarFive JH7110 drivers (2024-06-12 23:16:55 +0100) ---------------------------------------------------------------- RISC-V config update for v6.11 StarFive: Enable most of the options needed for the jh7100 based boards to be properly testable with defconfig. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Hal Feng (1): riscv: defconfig: Enable StarFive JH7110 drivers arch/riscv/configs/defconfig | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) --8e9vZ7cZueqeuYTs Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorQRgAKCRB4tDGHoIJi 0q2mAQCIlXjes04MsCW7Tk1ZKu26x6dn7lrn2YLHs7cy1Kt0ngD/Yca8ptVoIVNT I+DwPcZgC1lvwW/zu4C/q7gdgR4rTgw= =uqw1 -----END PGP SIGNATURE----- --8e9vZ7cZueqeuYTs-- --===============1361212987095751414== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============1361212987095751414==-- . Date: Sun, 7 Jul 2024 18:58:00 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V Devicetrees for v6.11 --===============9207122159081480999== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="4tXnFVVA6r14f/tL" Content-Disposition: inline --4tXnFVVA6r14f/tL Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Should be the final PR from me. I meant to send this stuff out end of last week but I ended up getting sick - and I'm going to blame screwing up my PR subjects on that... There's not really a huge amount in here, I ended up dropping the k230 that missed last window cos there's been no further interest in getting it support outside of the basic uart + interrupt controllers + memory configuration dts that Yangyu Chen sent. The board is fairly frustrating to work with due to the bootloader setup, and maybe nobody really cares since it's fairly underpowered, especially compared to the Spacemit k1 equipped Banana Pi board. I've stashed it in a branch in case anyone surfaces that cares about it. So no vector 1.0 hardware with a dts in the kernel yet. Cheers, Conor. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v6.11 for you to fetch changes up to 2904244a8c46bdd0fee181df693a495f4628a575: riscv: dts: starfive: add PCIe dts configuration for JH7110 (2024-07-01 13:20:19 +0100) ---------------------------------------------------------------- RISC-V Devicetrees for v6.11 T-Head: Last change from me before this starts going via Drew's tree is the addition of the SBI PMU events node for the th1520. StarFive: A dts for the Pin64 Star64, another board with a jh7110 SoC. This board is almost identical to the existing Milk-v Mars and VisionFive 2 boards that are already support - just with a different PHY configuration and only one of the two PCIe ports exposed. Additionally, the Mars and VisionFive 2 get their PCie configuration added. Microchip: A dts for the BeagleV Fire. PCIe is disabled on it for now, as some binding and driver changes are required. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (2): dt-bindings: riscv: microchip: document beaglev-fire riscv: dts: microchip: add an initial devicetree for the BeagleV Fire Henry Bell (2): dt-bindings: riscv: starfive: add Star64 board compatible riscv: dts: starfive: add Star64 board devicetree Inochi Amaoto (1): riscv: dts: thead: th1520: Add PMU event node Matthias Brugger (1): riscv: dts: starfive: Update flash partition layout Minda Chen (1): riscv: dts: starfive: add PCIe dts configuration for JH7110 Yangyu Chen (1): dt-bindings: riscv: Add T-HEAD C908 compatible Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/riscv/microchip.yaml | 1 + .../devicetree/bindings/riscv/starfive.yaml | 1 + arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-beaglev-fire-fabric.dtsi | 82 ++++++++ .../riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 223 +++++++++++++++++++++ arch/riscv/boot/dts/starfive/Makefile | 1 + arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 69 ++++++- arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts | 7 + .../boot/dts/starfive/jh7110-pine64-star64.dts | 65 ++++++ .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 ++++++++ arch/riscv/boot/dts/thead/th1520.dtsi | 81 ++++++++ 13 files changed, 621 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts --4tXnFVVA6r14f/tL Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZorXKAAKCRB4tDGHoIJi 0uo/AP98wGZ+35lf668q1VOJ3CAeMAkQwYt7AgPabvq7aO1hHAEAygP3TIHcsK/U RitSn2i8ioggSeskCNm5i3NtmHP+sA0= =SVga -----END PGP SIGNATURE----- --4tXnFVVA6r14f/tL-- --===============9207122159081480999== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============9207122159081480999==-- . Date: Tue, 9 Jul 2024 08:39:29 +0800 From: Chen Wang To: soc@kernel.org Cc: conor@kernel.org, arnd@arndb.de, linux-riscv@lists.infradead.org, inochiama@outlook.com, xiaoguang.xing@sophgo.com, haijiao.liu@sophgo.com, chao.wei@sophgo.com, unicorn_wang@outlook.com Subject: [GIT PULL] RISC-V Sophgo Devicetrees for v6.11 SGV5IEFybmQsCgpQbGVhc2UgcHVsbCBkdCBjaGFuZ2VzIGZvciBSSVNDLVYvU29waGdvLgoKSSBo b3BlIHRoaXMgUFIgaXMgbm90IHRvbyBsYXRlLCBiZWNhdXNlIEkganVzdCBnb3QgdGhlIG1lc3Nh Z2UgdG9kYXkgCmZyb20gU3RlcGhlbiB0aGF0IHRoaXMgY2xvY2sgZHJpdmVyIHBhcnQgaGFzIGJl ZW4gbWVyZ2VkIGludG8gY2xrLW5leHQuCgpKdXN0IEZZSTogCmh0dHBzOi8vbG9yZS5rZXJuZWwu b3JnL2xpbnV4LXJpc2N2L2I4ZGJkZGUyNDEyZDk3NGJhYTI0NjExYjE2Y2RhNWY3LnNib3lkQGtl cm5lbC5vcmcvCgoKVGhhbmtzLApDaGVuLgoKVGhlIGZvbGxvd2luZyBjaGFuZ2VzIHNpbmNlIGNv bW1pdCAxNjEzZTYwNGRmMGNkMzU5Y2YyYTdmYmQ5YmU3YTBiY2ZhY2ZhYmQwOgoKIMKgIExpbnV4 IDYuMTAtcmMxICgyMDI0LTA1LTI2IDE1OjIwOjEyIC0wNzAwKQoKYXJlIGF2YWlsYWJsZSBpbiB0 aGUgR2l0IHJlcG9zaXRvcnkgYXQ6CgogwqAgaHR0cHM6Ly9naXRodWIuY29tL3NvcGhnby9saW51 eC5naXQgdGFncy9yaXNjdi1zb3BoZ28tZHQtZm9yLXY2LjExCgpmb3IgeW91IHRvIGZldGNoIGNo YW5nZXMgdXAgdG8gYjEyNDBhMzk1MTFiOTIwNjI5M2I4MmFjMzcyYzUxMTRkNmUxNTgyMToKCiDC oCByaXNjdjogZHRzOiBhZGQgY2xvY2sgZ2VuZXJhdG9yIGZvciBTb3BoZ28gU0cyMDQyIFNvQyAo MjAyNC0wNy0wOSAKMDg6MTk6NTIgKzA4MDApCgotLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tClJJU0MtViBEZXZpY2V0cmVlcyBm b3IgdjYuMTEKClNvcGdobzoKQWRkIGNsb2NrIHN1cHBvcnQgZm9yIFNHMjA0Mi4KClNpZ25lZC1v ZmYtYnk6IENoZW4gV2FuZyA8dW5pY29ybl93YW5nQG91dGxvb2suY29tPgoKLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQpDaGVu IFdhbmcgKDEpOgogwqDCoMKgwqDCoCByaXNjdjogZHRzOiBhZGQgY2xvY2sgZ2VuZXJhdG9yIGZv ciBTb3BoZ28gU0cyMDQyIFNvQwoKIMKgYXJjaC9yaXNjdi9ib290L2R0cy9zb3BoZ28vc2cyMDQy LW1pbGt2LXBpb25lZXIuZHRzIHwgMTIgKysrKysrKysrKysrCiDCoGFyY2gvcmlzY3YvYm9vdC9k dHMvc29waGdvL3NnMjA0Mi5kdHNpwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfCA1NSAKKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLQogwqAy IGZpbGVzIGNoYW5nZWQsIDY2IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKCgoKCgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1yaXNjdiBt YWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMu aW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg== .