Date: Fri, 22 Jul 2022 08:52:11 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 5.19-rc8 merged tag 'dt-fixes-for-palmer-5.19-rc6' The following changes since commit 7fccd723912702acfc2d75e8f0596982534f7f24: Merge tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes (2022-07-13 10:44:22 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.19-rc8 for you to fetch changes up to c1f6eff304e4dfa4558b6a8c6b2d26a91db6c998: riscv: add as-options for modules with assembly compontents (2022-07-21 12:09:29 -0700) ---------------------------------------------------------------- RISC-V Fixes for 5.19-rc8 * Two kexec-related build fixes. * A DTS update to make the GPIO nodes match the upcoming dtschema. * A fix that passes -mno-relax directly to the assembler when building modules, to work around compilers that fail to do so. ---------------------------------------------------------------- Ben Dooks (1): riscv: add as-options for modules with assembly compontents Krzysztof Kozlowski (1): riscv: dts: align gpio-key node names with dtschema Li Zhengyu (2): RISCV: kexec: Fix build error without CONFIG_MODULES RISC-V: kexec: Fix build error without CONFIG_KEXEC arch/riscv/Makefile | 1 + arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 6 +++--- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/elf_kexec.c | 2 +- 8 files changed, 10 insertions(+), 9 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 29 Jul 2022 18:01:27 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv changes for 5.20 Hi Paolo, We have following KVM RISC-V changes for 5.20: 1) Track ISA extensions used by Guest using bitmap 2) Added system instruction emulation framework 3) Added CSR emulation framework 4) Added gfp_custom flag in struct kvm_mmu_memory_cache 5) Added G-stage ioremap() and iounmap() functions 6) Added support for Svpbmt inside Guest Please pull. Regards, Anup The following changes since commit e0dccc3b76fb35bb257b4118367a883073d7390e: Linux 5.19-rc8 (2022-07-24 13:26:27 -0700) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-5.20-1 for you to fetch changes up to 6bb2e00ea304ffc0446f345c46fe22713ce43cbf: RISC-V: KVM: Add support for Svpbmt inside Guest/VM (2022-07-29 17:15:18 +0530) ---------------------------------------------------------------- KVM/riscv changes for 5.20 - Track ISA extensions used by Guest using bitmap - Added system instruction emulation framework - Added CSR emulation framework - Added gfp_custom flag in struct kvm_mmu_memory_cache - Added G-stage ioremap() and iounmap() functions - Added support for Svpbmt inside Guest ---------------------------------------------------------------- Anup Patel (7): RISC-V: KVM: Factor-out instruction emulation into separate sources RISC-V: KVM: Add extensible system instruction emulation framework RISC-V: KVM: Add extensible CSR emulation framework KVM: Add gfp_custom flag in struct kvm_mmu_memory_cache RISC-V: KVM: Add G-stage ioremap() and iounmap() functions RISC-V: KVM: Use PAGE_KERNEL_IO in kvm_riscv_gstage_ioremap() RISC-V: KVM: Add support for Svpbmt inside Guest/VM Atish Patra (1): RISC-V: KVM: Improve ISA extension by using a bitmap Nikolay Borisov (2): RISC-V: KVM: Make kvm_riscv_guest_timer_init a void function RISC-V: KVM: move preempt_disable() call in kvm_arch_vcpu_ioctl_run Zhang Jiaming (1): RISC-V: KVM: Fix variable spelling mistake arch/riscv/include/asm/csr.h | 16 + arch/riscv/include/asm/kvm_host.h | 24 +- arch/riscv/include/asm/kvm_vcpu_fp.h | 8 +- arch/riscv/include/asm/kvm_vcpu_insn.h | 48 ++ arch/riscv/include/asm/kvm_vcpu_timer.h | 2 +- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/mmu.c | 28 +- arch/riscv/kvm/vcpu.c | 203 ++++++--- arch/riscv/kvm/vcpu_exit.c | 496 +-------------------- arch/riscv/kvm/vcpu_fp.c | 27 +- arch/riscv/kvm/vcpu_insn.c | 752 ++++++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu_timer.c | 4 +- arch/riscv/kvm/vm.c | 4 +- include/linux/kvm_types.h | 1 + include/uapi/linux/kvm.h | 8 + virt/kvm/kvm_main.c | 4 +- 17 files changed, 1028 insertions(+), 599 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_insn.h create mode 100644 arch/riscv/kvm/vcpu_insn.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 29 Jul 2022 10:05:21 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] A Single RISC-V Fix for 5.19 The following changes since commit c1f6eff304e4dfa4558b6a8c6b2d26a91db6c998: riscv: add as-options for modules with assembly compontents (2022-07-21 12:09:29 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.19-rc9 for you to fetch changes up to 88bd24d73d5bfa1b7b97a9221ff320fc44ef401a: riscv: compat: vdso: Fix vdso_install target (2022-07-22 12:23:14 -0700) ---------------------------------------------------------------- A Single RISC-V Fix for 5.19 * A build fix for "make vdso_install" that avoids an issue trying to install the compat VDSO. ---------------------------------------------------------------- Emil Renner Berthing (1): riscv: compat: vdso: Fix vdso_install target arch/riscv/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 05 Aug 2022 16:36:38 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 1 The following changes since commit 924cbb8cbe3460ea192e6243017ceb0ceb255b1b: riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol (2022-06-16 15:47:39 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw0 for you to fetch changes up to ba6cfef057e1c594c456627aad81c2343fdb5d13: riscv: enable Docker requirements in defconfig (2022-07-22 13:43:28 -0700) ---------------------------------------------------------------- RISC-V Patches for the 5.20 Merge Window, Part 1 * Enabling the FPU is now a static_key. * Improvements to the Svpbmt support. * CPU topology bindings for a handful of systems. * Support for systems with 64-bit hart IDs. * Many settings have been enabled in the defconfig, including both support for the StarFive systems and many of the Docker requirements. There are also a handful of cleanups and improvements, like usual. ---------------------------------------------------------------- This all passes my standard tests, with the old caveat that I'm still seeing some weirdness with QEMU-7.0 and a new issue where GCC-11 is tripping up on some fortify string checks in lm90.c on rv32 (GCC-12 works). I don't really like to send stuff when there's some outstanding issues like this, but after poking around for a bit it doesn't look like either is related to this pull request so it seems worse to hold off any longer. I'm also not 100% sure why it's calling out a patch in the middle as the base, I see v5.19-rc1 in the history. Sorry if something went off the rails there. I have one merge conflict, these defines were set to non-zero in arch/riscv at the same time the refactoring to make them generic went in. I'd considered merging that PR locally and making the fix in my tree, but that looked uglier than just passing the merge conflict on. Let me know if I should have done this the other way around, though. diff --cc arch/riscv/include/asm/pci.h index 830ac621dbbc,6ef4a1426194..cc2a184cfc2e --- a/arch/riscv/include/asm/pci.h +++ b/arch/riscv/include/asm/pci.h @@@ -12,31 -12,7 +12,10 @@@ #include +#define PCIBIOS_MIN_IO 4 +#define PCIBIOS_MIN_MEM 16 + - /* RISC-V shim does not initialize PCI bus */ - #define pcibios_assign_all_busses() 1 - - #define ARCH_GENERIC_PCI_MMAP_RESOURCE 1 - - extern int isa_dma_bridge_buggy; - - #ifdef CONFIG_PCI - static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) - { - /* no legacy IRQ on risc-v */ - return -ENODEV; - } - - static inline int pci_proc_domain(struct pci_bus *bus) - { - /* always show the domain in /proc */ - return 1; - } - - #ifdef CONFIG_NUMA - + #if defined(CONFIG_PCI) && defined(CONFIG_NUMA) static inline int pcibus_to_node(struct pci_bus *bus) { return dev_to_node(&bus->dev); ---------------------------------------------------------------- Celeste Liu (1): riscv: mmap with PROT_WRITE but no PROT_READ is invalid Conor Dooley (7): riscv: dts: microchip: remove spi-max-frequency property riscv: dts: microchip: Add mpfs' topology information riscv: config: enable SOC_STARFIVE in defconfig riscv: dts: sifive: Add fu540 topology information riscv: dts: sifive: Add fu740 topology information riscv: dts: canaan: Add k210 topology information riscv: dts: sifive: "fix" pmic watchdog node name Heiko Stuebner (4): riscv: make patch-function pointer more generic in cpu_manufacturer_info struct riscv: remove usage of function-pointers from cpufeatures and t-head errata riscv: introduce nops and __nops macros for NOP sequences riscv: convert the t-head pbmt errata to use the __nops macro Heinrich Schuchardt (1): riscv: enable Docker requirements in defconfig Jisheng Zhang (2): riscv: introduce unified static key mechanism for ISA extensions riscv: switch has_fpu() to the unified static key mechanism Jonas Hahnfeld (1): riscv: dts: starfive: Add JH7100 CPU topology Juerg Haefliger (3): riscv: Kconfig: Fix indentation and add comments riscv: Kconfig.erratas: Add comments riscv: Kconfig.socs: Add comments Maciej W. Rozycki (1): RISC-V: PCI: Avoid handing out address 0 to devices Nagasuresh Relli (1): riscv: dts: microchip: remove spi-max-frequency property Palmer Dabbelt (8): RISC-V: Use the extension probing code to enable the FPU RISC-V: Some Svpbmt fixes and cleanups riscv: Kconfig: Style cleanups RISC-V: Add CONFIG_{NON,}PORTABLE Merge tag 'dt-for-palmer-v5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into for-next Merge branch 'riscv-cpu_map_topo' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into for-next RISC-V: Support for 64bit hartid on RV64 platforms riscv: Add macro for multiple nop instructions Sunil V L (5): riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 riscv: spinwait: Fix hartid variable type riscv: smp: Add 64bit hartid support on RV64 riscv: cpu: Add 64bit hartid support on RV64 riscv/efi_stub: Add 64bit boot-hartid support on RV64 Xianting Tian (1): RISC-V: Add fast call path of crash_kexec() arch/riscv/Kconfig | 47 ++++++++++++---- arch/riscv/Kconfig.erratas | 2 +- arch/riscv/Kconfig.socs | 4 +- arch/riscv/boot/dts/canaan/k210.dtsi | 12 ++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 27 ++++++++- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 24 ++++++++ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 24 ++++++++ .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 2 +- arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 +++++- arch/riscv/configs/32-bit.config | 2 + arch/riscv/configs/defconfig | 65 +++++++++++++++++++++- arch/riscv/configs/nommu_k210_defconfig | 1 + arch/riscv/configs/nommu_k210_sdcard_defconfig | 1 + arch/riscv/configs/nommu_virt_defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + arch/riscv/errata/thead/errata.c | 38 ++++--------- arch/riscv/include/asm/asm.h | 15 +++++ arch/riscv/include/asm/barrier.h | 2 + arch/riscv/include/asm/errata_list.h | 8 +-- arch/riscv/include/asm/hwcap.h | 25 +++++++++ arch/riscv/include/asm/pci.h | 4 +- arch/riscv/include/asm/processor.h | 4 +- arch/riscv/include/asm/smp.h | 4 +- arch/riscv/include/asm/switch_to.h | 4 +- arch/riscv/kernel/alternative.c | 18 +++--- arch/riscv/kernel/cpu.c | 26 +++++---- arch/riscv/kernel/cpu_ops_sbi.c | 4 +- arch/riscv/kernel/cpu_ops_spinwait.c | 4 +- arch/riscv/kernel/cpufeature.c | 52 +++++++---------- arch/riscv/kernel/smp.c | 4 +- arch/riscv/kernel/smpboot.c | 9 +-- arch/riscv/kernel/sys_riscv.c | 5 +- arch/riscv/kernel/traps.c | 4 ++ drivers/clocksource/timer-riscv.c | 15 ++--- drivers/firmware/efi/libstub/riscv-stub.c | 13 ++++- drivers/irqchip/irq-riscv-intc.c | 7 ++- drivers/irqchip/irq-sifive-plic.c | 7 ++- 37 files changed, 358 insertions(+), 143 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Wed, 10 Aug 2022 15:02:42 +0100 From: Conor Dooley To: , Daire McNamara Subject: [RESEND/PULL PATCH 0/2] MAINTAINERS updates for PolarFire SoC Hey Arnd, Could you please take the following two patches via the soc tree when you get a chance? The first is adding coverage for "my" dt-bindings as suggested by Mark. I CCed all the subsystem maintainers on a V1 a week ago & I've added them explicity to the patch text this time as CCs. Correct me if I am wrong, but I am operating on the assumption that their Acks are not required here. Hopefully increasing the binding coverage is non controversial! The second patch is a resend of a patch that was deferred to later in the merge window avoid messing about with a 4th conflict in the entry. Thanks, Conor. Conor Dooley (2): MAINTAINERS: add PolarFire SoC dt bindings MAINTAINERS: add the Polarfire SoC's i2c driver MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) base-commit: 4e23eeebb2e57f5a28b36221aa776b5a1122dde5 -- 2.36.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 12 Aug 2022 17:37:06 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Patches for the 5.20 Merge Window, Part 2 The following changes since commit 4d1044fcb996e8de9b9ab392f4a767890e45202d: Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2022-08-06 15:04:48 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.20-mw2 for you to fetch changes up to 5cef38dd03f33ef206eb792df0fb3b200d762546: dt-bindings: gpio: sifive: add gpio-line-names (2022-08-12 09:00:01 -0700) ---------------------------------------------------------------- RISC-V Patches for the 5.20 Merge Window, Part 2 There's still a handful of new features in here, but there are a lot of fixes/cleanups as well: * Support for the Zicbom for explicit cache-block management, along with the necessary bits to make the non-standard cache management ops on the Allwinner D1 function. * Support for the Zihintpause extension, which codifies a go-slow instruction used for cpu_relax(). * Support for the Sstc extension for supervisor-mode timer/counter management. * Many device tree fixes and cleanups, including a large set for the Canaan device trees. * A handful of fixes and cleanups for the PMU driver. ---------------------------------------------------------------- These all pass for me, but they do require some sparse patches that I just posted to handle the new ISA strings. There are a handful of warnings, but they're all in various stages of being fixed and the only one that's reproducing locally for me is the bluetooth issue that's not related to any of these. ---------------------------------------------------------------- Atish Patra (9): RISC-V: Add SSTC extension CSR details RISC-V: Enable sstc extension parsing from DT RISC-V: Prefer sstc extension if available RISC-V: Fix counter restart during overflow for RV32 RISC-V: Update user page mapping only once during start RISC-V: Fix SBI PMU calls for RV32 RISC-V: Move counter info definition to sbi header file RISC-V: Improve SBI definitions RISC-V: KVM: Support sstc extension Atul Khare (1): dt-bindings: gpio: sifive: add gpio-line-names Ben Dooks (2): RISC-V: Declare cpu_ops_spinwait in RISC-V: cpu_ops_spinwait.c should include head.h Chen Lifu (1): riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit Conor Dooley (14): dt-bindings: display: convert ilitek,ili9341.txt to dt-schema dt-bindings: display: ili9341: document canaan kd233's lcd dt-bindings: memory-controllers: add canaan k210 sram controller riscv: dts: canaan: fix the k210's memory node riscv: dts: canaan: fix the k210's timer nodes riscv: dts: canaan: fix mmc node names riscv: dts: canaan: fix kd233 display spi frequency riscv: dts: canaan: use custom compatible for k210 i2s riscv: dts: canaan: remove spi-max-frequency from controllers riscv: dts: canaan: fix bus {ranges,reg} warnings riscv: dts: canaan: add specific compatible for kd233's LCD riscv: dts: canaan: build all devicetress if SOC_CANAAN riscv: ensure cpu_ops_sbi is declared dt-bindings: riscv: fix SiFive l2-cache's cache-sets Dao Lu (1): arch/riscv: add Zihintpause support Emil Renner Berthing (1): riscv: dts: sifive unmatched: Add PWM controlled LEDs Heiko Stuebner (4): of: also handle dma-noncoherent in of_dma_is_coherent() dt-bindings: riscv: document cbom-block-size riscv: Add support for non-coherent devices using zicbom extension riscv: implement cache-management errata for T-Head SoCs Jason A. Donenfeld (1): wireguard: selftests: set CONFIG_NONPORTABLE on riscv32 Krzysztof Kozlowski (1): riscv: traps_misaligned: do not duplicate stringify Mark Kettenis (1): riscv: dts: starfive: correct number of external interrupts Masahiro Yamada (2): riscv/purgatory: hard-code obj-y in Makefile riscv/purgatory: Omit use of bin2c Palmer Dabbelt (5): RISC-V: Canaan devicetree fixes riscv: implement Zicbom-based CMO instructions + the t-head variant RISC-V: fixups to work with crash tool RISC-V: Add Sstc extension support perf: riscv_pmu{,_sbi}: Miscallenous improvement & fixes Xianting Tian (4): RISC-V: kexec: Fixup use of smp_processor_id() in preemptible context RISC-V: Fixup get incorrect user mode PC for kernel mode regs RISC-V: Fixup schedule out issue in machine_crash_shutdown() RISC-V: Add modules to virtual kernel memory layout dump Yipeng Zou (1): riscv:uprobe fix SR_SPIE set/clear handling .../devicetree/bindings/display/ilitek,ili9341.txt | 27 ---- .../bindings/display/panel/ilitek,ili9341.yaml | 49 +++++-- .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 + .../memory-controllers/canaan,k210-sram.yaml | 52 ++++++++ Documentation/devicetree/bindings/riscv/cpus.yaml | 5 + .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 6 +- arch/riscv/Kconfig | 32 ++++- arch/riscv/Kconfig.erratas | 11 ++ arch/riscv/Makefile | 8 ++ arch/riscv/boot/dts/canaan/Makefile | 10 +- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 6 +- arch/riscv/boot/dts/canaan/k210.dtsi | 73 +++++++---- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 42 ++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +- arch/riscv/errata/thead/errata.c | 20 +++ arch/riscv/include/asm/cache.h | 4 + arch/riscv/include/asm/cacheflush.h | 10 ++ arch/riscv/include/asm/cpu_ops.h | 1 + arch/riscv/include/asm/cpu_ops_sbi.h | 2 + arch/riscv/include/asm/csr.h | 5 + arch/riscv/include/asm/errata_list.h | 59 ++++++++- arch/riscv/include/asm/hwcap.h | 7 + arch/riscv/include/asm/kvm_vcpu_timer.h | 7 + arch/riscv/include/asm/sbi.h | 32 ++++- arch/riscv/include/asm/vdso/processor.h | 21 ++- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kernel/cpu.c | 3 + arch/riscv/kernel/cpu_ops.c | 5 +- arch/riscv/kernel/cpu_ops_spinwait.c | 2 + arch/riscv/kernel/cpufeature.c | 26 ++++ arch/riscv/kernel/crash_save_regs.S | 2 +- arch/riscv/kernel/machine_kexec.c | 28 +++- arch/riscv/kernel/probes/uprobes.c | 6 - arch/riscv/kernel/setup.c | 2 + arch/riscv/kernel/traps_misaligned.c | 8 +- arch/riscv/kvm/vcpu.c | 8 +- arch/riscv/kvm/vcpu_timer.c | 144 ++++++++++++++++++++- arch/riscv/lib/uaccess.S | 4 +- arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 116 +++++++++++++++++ arch/riscv/mm/init.c | 4 + arch/riscv/purgatory/.gitignore | 1 - arch/riscv/purgatory/Makefile | 10 +- arch/riscv/purgatory/kexec-purgatory.S | 14 ++ drivers/clocksource/timer-riscv.c | 25 +++- drivers/of/address.c | 17 ++- drivers/perf/riscv_pmu.c | 1 - drivers/perf/riscv_pmu_sbi.c | 30 +++-- scripts/remove-stale-files | 2 + .../selftests/wireguard/qemu/arch/riscv32.config | 1 + 54 files changed, 821 insertions(+), 143 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml create mode 100644 arch/riscv/mm/dma-noncoherent.c create mode 100644 arch/riscv/purgatory/kexec-purgatory.S _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Mon, 15 Aug 2022 22:14:55 +0000 From: To: , , , Subject: [GIT PULL] Fix RISC-V's arch-topology reporting Hey Will/Palmer/Sudeep, Catalin suggested [0] dropping the CC: stable for the arm64 patch and instead making it a specific prereq of the RISC-V patch & making a PR, so here we are.. I was still up when -rc1 came out so pushed it last night to get the test coverage, but LKP seems to not have reported a build success since early on the 13th so not holding my horses! I built it again for both ARMs and RISC-V myself. I tagged it tonight, so it's on conor/linux.git as riscv-topo-on-6.0-rc1 with the prereq specified. Not sure if you want to merge this too Sudeep or if that's up to Greg? Thanks, Conor. 0 - https://lore.kernel.org/linux-riscv/Ytac7G1zlq6WW4jt@arm.com/ The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-topo-on-6.0-rc1 for you to fetch changes up to fbd92809997a391f28075f1c8b5ee314c225557c: riscv: topology: fix default topology reporting (2022-08-15 22:07:34 +0100) ---------------------------------------------------------------- Fix RISC-V's topology reporting The goal here is the fix the incorrectly reported arch topology on RISC-V which seems to have been broken since it was added. cpu, package and thread IDs are all currently reported as -1, so tools like lstopo think systems have multiple threads on the same core when this is not true: https://github.com/open-mpi/hwloc/issues/536 arm64's topology code basically applies to RISC-V too, so it has been made generic along with the removal of MPIDR related code, which appears to be redudant code since '3102bc0e6ac7 ("arm64: topology: Stop using MPIDR for topology information")' replaced the code that actually interacted with MPIDR with default values. ---------------------------------------------------------------- Conor Dooley (2): arm64: topology: move store_cpu_topology() to shared code riscv: topology: fix default topology reporting arch/arm64/kernel/topology.c | 40 ---------------------------------------- arch/riscv/Kconfig | 2 +- arch/riscv/kernel/smpboot.c | 3 ++- drivers/base/arch_topology.c | 19 +++++++++++++++++++ 4 files changed, 22 insertions(+), 42 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 19 Aug 2022 09:28:44 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 6.0-rc2 The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc2 for you to fetch changes up to 96264230a6817bcd4a7ae0fc30c60bfb46499f68: perf: riscv legacy: fix kerneldoc comment warning (2022-08-18 14:19:26 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.0-rc2 * A fix to make the ISA extension static keys writable after init. This manifests at least as a crash when loading modules (including KVM). * A fixup for a build warning related to a poorly formed comment in our perf driver. ---------------------------------------------------------------- Andrew Jones (1): riscv: Ensure isa-ext static keys are writable Conor Dooley (1): perf: riscv legacy: fix kerneldoc comment warning arch/riscv/kernel/cpufeature.c | 2 +- drivers/perf/riscv_pmu_legacy.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Sat, 20 Aug 2022 13:31:55 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv fixes for 6.0, take #1 Hi Paolo, We have two minor fixes for 6.0: 1) Fix unused variable warnings in vcpu_timer.c 2) Move extern sbi_ext declarations to a header Please pull. Regards, Anup The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-fixes-6.0-1 for you to fetch changes up to 3e5e56c60a14776e2a49837b55b03bc193fd91f7: riscv: kvm: move extern sbi_ext declarations to a header (2022-08-19 23:22:47 +0530) ---------------------------------------------------------------- KVM/riscv fixes for 6.0, take #1 - Fix unused variable warnings in vcpu_timer.c - Move extern sbi_ext declarations to a header ---------------------------------------------------------------- Conor Dooley (2): riscv: kvm: vcpu_timer: fix unused variable warnings riscv: kvm: move extern sbi_ext declarations to a header arch/riscv/include/asm/kvm_vcpu_sbi.h | 12 ++++++++++++ arch/riscv/kvm/vcpu_sbi.c | 12 +----------- arch/riscv/kvm/vcpu_timer.c | 4 ---- 3 files changed, 13 insertions(+), 15 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Thu, 25 Aug 2022 18:17:45 +0000 From: To: Subject: [GIT PULL] Microchip RISC-V devicetree fixes for 6.0-rc3 Hey Palmer, Couple fixes here for -rc3.. Notably the patch from Heinrich as it stops the console being /flooded/ by error messages from the l2 cache controller's interrupt handler. Unfortunately, that fix brought with it another dtbs_check warning for which I have submitted patches: https://lore.kernel.org/linux-riscv/20220825180417.1259360-1-mail@conchuod.ie On track for zero warnings in v6.1 though, patches are applied for the others in the pci tree. Thanks, Conor. The following changes since commit 69dac8e431af26173ca0a1ebc87054e01c585bcc: Merge tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2022-08-12 18:39:43 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/dt-fixes-for-palmer-6.0-rc3 for you to fetch changes up to e4009c5fa77b4356aa37ce002e9f9952dfd7a615: riscv: dts: microchip: mpfs: remove pci axi address translation property (2022-08-23 22:15:55 +0100) ---------------------------------------------------------------- Microchip RISC-V devicetree fixes for 6.0-rc3 Two sets of fixes this time around: - A fix for the interrupt ordering of the l2-cache controller. If the driver is enabled, it would spam the console /constantly/, rendering the system useless. - General cleanup for some bogus properties in the dt, part of my quest for zero dtbs_check warnings. On that note, the interrupt ordering adds a dtbs_check warning - but I considered that fixing the potentially useless system was more of a priority. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (4): riscv: dts: microchip: mpfs: fix incorrect pcie child node name riscv: dts: microchip: mpfs: remove ti,fifo-depth property riscv: dts: microchip: mpfs: remove bogus card-detect-delay riscv: dts: microchip: mpfs: remove pci axi address translation property Heinrich Schuchardt (1): riscv: dts: microchip: correct L2 cache interrupts arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 --- arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 3 --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 5 ++--- 3 files changed, 2 insertions(+), 9 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 26 Aug 2022 09:01:28 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 6.0-rc3 The following changes since commit 96264230a6817bcd4a7ae0fc30c60bfb46499f68: perf: riscv legacy: fix kerneldoc comment warning (2022-08-18 14:19:26 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc3 for you to fetch changes up to 1709c70c31e05e6e87b2ffa0a2b4cc0da4b2c513: Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (2022-08-25 16:38:01 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.0-rc3 * A handful of fixes for the Microchip device trees. * A pair of fixes to eliminate build warnings. ---------------------------------------------------------------- Conor Dooley (6): riscv: signal: fix missing prototype warning riscv: traps: add missing prototype riscv: dts: microchip: mpfs: fix incorrect pcie child node name riscv: dts: microchip: mpfs: remove ti,fifo-depth property riscv: dts: microchip: mpfs: remove bogus card-detect-delay riscv: dts: microchip: mpfs: remove pci axi address translation property Heinrich Schuchardt (1): riscv: dts: microchip: correct L2 cache interrupts Palmer Dabbelt (2): Merge tag 'dt-fixes-for-palmer-6.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 --- arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 3 --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 5 ++--- arch/riscv/include/asm/signal.h | 12 ++++++++++++ arch/riscv/include/asm/thread_info.h | 2 ++ arch/riscv/kernel/signal.c | 1 + arch/riscv/kernel/traps.c | 3 ++- 7 files changed, 19 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/include/asm/signal.h _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 2 Sep 2022 16:07:49 +0000 From: To: Subject: [GIT PULL] Microchip DT fixes for v6.0-rc4 (or later) Hey Palmer, Two patches here that are really not particularly urgent by themselves. Both fix the interrupts dtbs_check warning that I introduced last week. As I said on my application mail: "patches for this dt-binding are usually merged via the riscv tree so I have taken the liberty of bundling it with the dts change". I would have sat on this for a little & grouped it with some other stuff, but Zong Li wants to do a rename of the binding [0] so to make life easier for them (and avoid this change being clobbered...) I decided to send this to you this week. I did not bother marking it CC: stable since it's just a binding checker warning - to be honest, I'd have sent it via for-next if not for the fact that the warning fixed by these patches went via fixes and I didn't want tooling screaming at me for invalid Fixes: tags.. If you wish to apply these patches to for-next instead, they are at: https://lore.kernel.org/linux-riscv/20220825180417.1259360-1-mail@conchuod.ie/ Thanks, Conor. The following changes since commit 1709c70c31e05e6e87b2ffa0a2b4cc0da4b2c513: Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (2022-08-25 16:38:01 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/dt-fixes-for-palmer-6.0-rc4 for you to fetch changes up to 0dec364ffeb6149aae572ded1e34d4b444c23be6: riscv: dts: microchip: use an mpfs specific l2 compatible (2022-08-31 16:57:51 +0100) ---------------------------------------------------------------- Microchip RISC-V devicetree fixes for 6.0-rc4 (or later) A fix for the warnings introduced in rc3 as part of fixing the console spam from the L2's isr. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (2): dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible riscv: dts: microchip: use an mpfs specific l2 compatible Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml | 79 +++++++++++++++++++++++++++++++++++++++++++++++++------------------------------ arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 2 files changed, 50 insertions(+), 31 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 09 Sep 2022 07:20:17 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 6.0-rc5 The following changes since commit 1709c70c31e05e6e87b2ffa0a2b4cc0da4b2c513: Merge branch 'riscv-variable_fixes_without_kvm' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git into fixes (2022-08-25 16:38:01 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc5 for you to fetch changes up to 20e0fbab16003ae23a9e86a64bcb93e3121587ca: perf: RISC-V: fix access beyond allocated array (2022-09-08 13:50:25 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.0-rc5 * A pair of device tree fixes for the Polarfire SOC. * A fix to avoid overflowing the PMU counter array when firmware incorrectly reports the number of supported counters, which manifests on OpenSBI versions prior to 1.1. ---------------------------------------------------------------- Conor Dooley (2): dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible riscv: dts: microchip: use an mpfs specific l2 compatible Palmer Dabbelt (1): Merge tag 'dt-fixes-for-palmer-6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes Sergey Matyukevich (1): perf: RISC-V: fix access beyond allocated array .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++++-------- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- drivers/perf/riscv_pmu_sbi.c | 2 +- 3 files changed, 51 insertions(+), 32 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 16 Sep 2022 08:31:19 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 6.0-rc6 The following changes since commit 20e0fbab16003ae23a9e86a64bcb93e3121587ca: perf: RISC-V: fix access beyond allocated array (2022-09-08 13:50:25 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc6 for you to fetch changes up to 5b5f6556027ccb04c731988923c051fd2b2bad18: RISC-V: Avoid coupling the T-Head CMOs and Zicbom (2022-09-16 02:59:06 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.0-rc6 * A handful of build fixes for the T-Head errata, including some functional issues the compilers found. * A fix to avoid bad page permission initialization, which manifests on systems that may load modules early. * A fix for a nasty sigreturn bug. ---------------------------------------------------------------- I have one merge conflict as a result of a treewide fix, I'm getting some odd output from just showing the merge (it's showing some of the fix too), but I think the merge itself is OK. My fix is to keep the write lock - mmap_read_lock(mm); ++ mmap_write_lock(mm); + ret = walk_page_range_novma(mm, start, end, &pageattr_ops, NULL, + &masks); - mmap_read_unlock(mm); ++ mmap_write_unlock(mm); ---------------------------------------------------------------- Al Viro (1): riscv: fix a nasty sigreturn bug... Heiko Stuebner (1): riscv: make t-head erratas depend on MMU Palmer Dabbelt (2): RISC-V: Clean up the Zicbom block size probing RISC-V: Avoid coupling the T-Head CMOs and Zicbom Randy Dunlap (1): riscv: fix RISCV_ISA_SVPBMT kconfig dependency warning Vladimir Isaev (1): riscv: Fix permissions for all mm's during mm init arch/riscv/Kconfig | 1 + arch/riscv/Kconfig.erratas | 4 +-- arch/riscv/errata/thead/errata.c | 1 + arch/riscv/include/asm/cacheflush.h | 5 +++ arch/riscv/include/asm/set_memory.h | 20 +++--------- arch/riscv/kernel/setup.c | 13 +------- arch/riscv/kernel/signal.c | 2 ++ arch/riscv/mm/dma-noncoherent.c | 23 ++++++++------ arch/riscv/mm/init.c | 29 ++++++++++++++--- arch/riscv/mm/pageattr.c | 62 ++++++++++++++++++++++++++++++++----- 10 files changed, 107 insertions(+), 53 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 23 Sep 2022 04:23:28 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 6.0-rc7 The following changes since commit 20e0fbab16003ae23a9e86a64bcb93e3121587ca: perf: RISC-V: fix access beyond allocated array (2022-09-08 13:50:25 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.0-rc7 for you to fetch changes up to c589e3ca27c9f608004b155d3acb2fab6f7a9f26: RISC-V: Avoid coupling the T-Head CMOs and Zicbom (2022-09-17 01:48:24 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.0-rc7 * A handful of build fixes for the T-Head errata, including some functional issues the compilers found. * A fix for a nasty sigreturn bug. ---------------------------------------------------------------- Sorry in advance if something else has gone off the rails on this one, I had a bit of an unplanned vacation this week and it's shaping up to be more tiring than the conferences. This is just what was there last week (without the deadlock), I figured it'd be best to avoid delaying those any longer. With any luck I'll be home tomorrow, so things should return to sanity soon-ish. ---------------------------------------------------------------- Al Viro (1): riscv: fix a nasty sigreturn bug... Heiko Stuebner (1): riscv: make t-head erratas depend on MMU Palmer Dabbelt (2): RISC-V: Clean up the Zicbom block size probing RISC-V: Avoid coupling the T-Head CMOs and Zicbom Randy Dunlap (1): riscv: fix RISCV_ISA_SVPBMT kconfig dependency warning arch/riscv/Kconfig | 1 + arch/riscv/Kconfig.erratas | 4 ++-- arch/riscv/errata/thead/errata.c | 1 + arch/riscv/include/asm/cacheflush.h | 5 +++++ arch/riscv/kernel/setup.c | 2 +- arch/riscv/kernel/signal.c | 2 ++ arch/riscv/mm/dma-noncoherent.c | 23 +++++++++++++---------- 7 files changed, 25 insertions(+), 13 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Sun, 2 Oct 2022 11:16:24 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv changes for 6.1 Hi Paolo, We have the following KVM RISC-V changes for 6.1: 1) Improved instruction encoding infrastructure for instructions not yet supported by binutils 2) Svinval support for both KVM Host and KVM Guest 3) Zihintpause support for KVM Guest 4) Zicbom support for KVM Guest 5) Record number of signal exits as a VCPU stat 6) Use generic guest entry infrastructure Please pull. Regards, Anup The following changes since commit f76349cf41451c5c42a99f18a9163377e4b364ff: Linux 6.0-rc7 (2022-09-25 14:01:02 -0700) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-6.1-1 for you to fetch changes up to b60ca69715fcc39a5f4bdd56ca2ea691b7358455: riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK (2022-10-02 10:19:31 +0530) ---------------------------------------------------------------- KVM/riscv changes for 6.1 - Improved instruction encoding infrastructure for instructions not yet supported by binutils - Svinval support for both KVM Host and KVM Guest - Zihintpause support for KVM Guest - Zicbom support for KVM Guest - Record number of signal exits as a VCPU stat - Use generic guest entry infrastructure ---------------------------------------------------------------- Andrew Jones (7): riscv: Add X register names to gpr-nums riscv: Introduce support for defining instructions riscv: KVM: Apply insn-def to hfence encodings riscv: KVM: Apply insn-def to hlv encodings RISC-V: KVM: Make ISA ext mappings explicit RISC-V: KVM: Provide UAPI for Zicbom block size RISC-V: KVM: Expose Zicbom to the guest Anup Patel (3): RISC-V: KVM: Change the SBI specification version to v1.0 RISC-V: KVM: Use Svinval for local TLB maintenance when available RISC-V: KVM: Allow Guest use Svinval extension Jisheng Zhang (3): RISC-V: KVM: Record number of signal exits as a vCPU stat RISC-V: KVM: Use generic guest entry infrastructure riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Mayuresh Chitale (2): RISC-V: Probe Svinval extension form ISA string RISC-V: KVM: Allow Guest use Zihintpause extension Xiu Jianfeng (1): RISC-V: KVM: add __init annotation to riscv_kvm_init() arch/riscv/Kconfig | 4 + arch/riscv/include/asm/gpr-num.h | 8 ++ arch/riscv/include/asm/hwcap.h | 4 + arch/riscv/include/asm/insn-def.h | 137 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/include/asm/kvm_vcpu_sbi.h | 4 +- arch/riscv/include/uapi/asm/kvm.h | 4 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/main.c | 2 +- arch/riscv/kvm/tlb.c | 155 +++++++++++----------------------- arch/riscv/kvm/vcpu.c | 60 ++++++++----- arch/riscv/kvm/vcpu_exit.c | 39 ++------- arch/riscv/mm/dma-noncoherent.c | 2 + 15 files changed, 260 insertions(+), 163 deletions(-) create mode 100644 arch/riscv/include/asm/insn-def.h _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 07 Oct 2022 10:47:57 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Patches for the 6.1 Merge Window, Part 1 The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.1-mw1 for you to fetch changes up to 87f81e66e2e84c7e6056413703d732a99c20c09b: riscv: enable THP_SWAP for RV64 (2022-10-06 20:03:48 -0700) ---------------------------------------------------------------- RISC-V Patches for the 6.1 Merge Window, Part 1 * Improvements to the CPU topology subsystem, which fix some issues where RISC-V would report bad topology information. * The default NR_CPUS has increased to XLEN, and the maximum configurable value is 512. * The CD-ROM filesystems have been enabled in the defconfig. * Support for THP_SWAP has been added for rv64 systems. There are also a handful of cleanups and fixes throughout the tree. ---------------------------------------------------------------- I will almost certainly have a part 2 for next week, but I'm not sure how big it will be: between the conferences and COVID things have been a mess on my end, that's clearly made this first week pretty small but it's also meant a lot of stuff on the lists still needs work. There's also some stuff that's pending on conflicts, though, so I figured it'd be best to just send this today to make handling those easier. I'm still seeing some of these KASAN/pcpu_alloc related panics, but it doesn't seem like they're more common with these than they are on 6.0 so I think it's OK to just call these safe. Aside from that things seem fine with this merged into master from this morning. ---------------------------------------------------------------- Anup Patel (2): cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz() macro usage RISC-V: Increase range and default value of NR_CPUS Conor Dooley (2): arm64: topology: move store_cpu_topology() to shared code riscv: topology: fix default topology reporting Heinrich Schuchardt (1): riscv: enable CD-ROM file systems in defconfig Jisheng Zhang (2): riscv: compat: s/failed/unsupported if compat mode isn't supported riscv: enable THP_SWAP for RV64 Palmer Dabbelt (2): Merge tag 'riscv-topo-on-6.0-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ into for-next RISC-V: Print SSTC in canonical order Sergey Matyukevich (2): perf: RISC-V: exclude invalid pmu counters from SBI calls perf: RISC-V: throttle perf events arch/arm64/kernel/topology.c | 40 ------------------------------------- arch/riscv/Kconfig | 12 +++++++---- arch/riscv/configs/defconfig | 3 +++ arch/riscv/kernel/cpu.c | 2 +- arch/riscv/kernel/process.c | 2 +- arch/riscv/kernel/smpboot.c | 3 ++- drivers/base/arch_topology.c | 19 ++++++++++++++++++ drivers/cpuidle/cpuidle-riscv-sbi.c | 7 ++++++- drivers/perf/riscv_pmu_legacy.c | 4 ++-- drivers/perf/riscv_pmu_sbi.c | 31 ++++++++++++++++++---------- include/linux/perf/riscv_pmu.h | 2 +- 11 files changed, 63 insertions(+), 62 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Mon, 10 Oct 2022 23:17:03 +0100 From: Conor Dooley To: Palmer Dabbelt Cc: Conor Dooley , linux-riscv@lists.infradead.org Subject: [GIT PULL 0/2] microchip maintainers updates From: Conor Dooley Hey Palmer, Two maintainers changes that I posted on the lists a while back. Neither applied at the time b/c the maintainers entry was being updated in the soc fixes branch and in some for-next branches at the same time and they conflicted. If you could pick the two that'd be great. Thanks, Conor. Conor Dooley (2): MAINTAINERS: update polarfire soc clock binding dt-bindings: riscv: update microchip.yaml's maintainership Documentation/devicetree/bindings/riscv/microchip.yaml | 4 ++-- MAINTAINERS | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) -- 2.37.3 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Wed, 12 Oct 2022 17:29:09 +0100 From: Conor Dooley To: palmer@dabbelt.com Cc: conor.dooley@microchip.com, linux-riscv@lists.infradead.org Subject: [GIT PULL] Microchip DT for v6.1 Hey Palmer, Late as previously mentioned since I had to wait for the reference design to actually get released - there's an -rc1 up on GitHub for it now that people can actually use :) It's all been in linux-next for a while, apart from the HEAD commit that is a fix I added last week rather than send you something I knew was wrong. There's one conflict between this PR and some stuff I sent via fixes, but the resolution should be easy. The commit on -fixes deleted the microchip,matr0 property from the PCI node & when I moved the PCI node into the -fabric.dtsi I accounted for that removal. The correct resolution is to take this PR's version & remove the node from mpfs.dtsi. Thanks, Conor. The following changes since commit 69dac8e431af26173ca0a1ebc87054e01c585bcc: Merge tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2022- 08-12 18:39:43 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/dt-for-palmer-v6.1-mw1 for you to fetch changes up to c210b91818e81068ca2573c20684644b8e110a07: riscv: dts: microchip: fix fabric i2c reg size (2022-10-07 13:43:42 +0100) ---------------------------------------------------------------- Microchip RISC-V devicetrees for v6.1 Fixups, reference design changes and new boards: - The addition of QSPI support for mpfs had a corresponding change to the devicetree node. - The v2022.{09,10} reference designs brought with them several memory map changes which are not backwards compatible. The old devicetrees from the v2022.08 and earlier releases still work with current kernels. - Two new devicetrees for a first-party development kit and for the Aries Embedded M100FPSEVP kit. - Corresponding dt-bindings changes for the above. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (11): riscv: dts: microchip: add qspi compatible fallback dt-bindings: riscv: microchip: document icicle reference design dt-bindings: riscv: microchip: document the aries m100pfsevp riscv: dts: microchip: add pci dma ranges for the icicle kit riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: reduce the fic3 clock rate riscv: dts: microchip: add a devicetree for aries' m100pfsevp riscv: dts: microchip: update memory configuration for v2022.10 riscv: dts: microchip: fix fabric i2c reg size Shravan Chippa (1): dt-bindings: riscv: microchip: document the sev kit Vattipalli Praveen (1): riscv: dts: microchip: add sevkit device tree Documentation/devicetree/bindings/riscv/microchip.yaml | 20 +++-- arch/riscv/boot/dts/microchip/Makefile | 2 + arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 43 ++++++++-- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 18 +++- arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 ++++++++++ arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++++++++++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++ arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++++++ arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 32 +------ 10 files changed, 512 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 14 Oct 2022 09:35:43 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Patches for the 6.1 Merge Window, Part 2 merged tag 'riscv-for-linus-6.1-mw1' The following changes since commit 2e64066dab157ffcd0e9ec2ff631862e6e222876: Merge tag 'riscv-for-linus-6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux (2022-10-09 13:24:01 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.1-mw2 for you to fetch changes up to ab0c23b535f3f9d8345d8ad4c18c0a8594459d55: MAINTAINERS: add RISC-V's patchwork (2022-10-13 16:35:25 -0700) ---------------------------------------------------------------- RISC-V Patches for the 6.1 Merge Window, Part 2 * A handful of DT updates for the PolarFire SOC. * A fix to correct the handling of write-only mappings. * m{vetndor,arcd,imp}id is now in /proc/cpuinfo * The SiFive L2 cache controller support has been refactored to also support L3 caches. There's also a handful of fixes, cleanups and improvements throughout the tree. ---------------------------------------------------------------- We still have these kasan/pcpu_alloc panics, but by all appearances the bug has been around for a while so it's not the fault of any of these (even if it just started manifesting very often for me in the middle of the merge window). I've got that and a build fix for drm/amd/display in my test trees, but otherwise things seem clean on my end. I've got one merge conflict with a master from last night, just a pair of cleanups that happened to run into each other. Here's my resolution if it helps any: diff --cc arch/riscv/kernel/vdso.c index 4abc9aebdfae,692e7ae3dcb8..123d05255fcf --- a/arch/riscv/kernel/vdso.c +++ b/arch/riscv/kernel/vdso.c @@@ -119,18 -114,16 +119,19 @@@ int vdso_join_timens(struct task_struc { struct mm_struct *mm = task->mm; struct vm_area_struct *vma; + VMA_ITERATOR(vmi, mm, 0); - struct __vdso_info *vdso_info = mm->context.vdso_info; mmap_read_lock(mm); - for (vma = mm->mmap; vma; vma = vma->vm_next) { + for_each_vma(vmi, vma) { unsigned long size = vma->vm_end - vma->vm_start; - if (vma_is_special_mapping(vma, vdso_info->dm)) + if (vma_is_special_mapping(vma, vdso_info.dm)) zap_page_range(vma, vma->vm_start, size); +#ifdef CONFIG_COMPAT + if (vma_is_special_mapping(vma, compat_vdso_info.dm)) + zap_page_range(vma, vma->vm_start, size); +#endif } mmap_read_unlock(mm); Sorry it's another big one late in the merge window, I'm trying to not do that but things keep slipping. ---------------------------------------------------------------- Andrew Bresticker (2): riscv: Make VM_WRITE imply VM_READ riscv: Allow PROT_WRITE-only mmap() Anup Patel (1): RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output Ben Dooks (2): soc: sifive: ccache: reduce printing on init soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Conor Dooley (18): riscv: dts: microchip: add qspi compatible fallback dt-bindings: riscv: microchip: document icicle reference design dt-bindings: riscv: microchip: document the aries m100pfsevp riscv: dts: microchip: add pci dma ranges for the icicle kit riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: reduce the fic3 clock rate riscv: dts: microchip: add a devicetree for aries' m100pfsevp riscv: dts: microchip: update memory configuration for v2022.10 riscv: dts: microchip: fix fabric i2c reg size MAINTAINERS: update polarfire soc clock binding dt-bindings: riscv: update microchip.yaml's maintainership dt-bindings: timer: sifive,clint: add legacy riscv compatible dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible dt-bindings: riscv: add new riscv,isa strings for emulators riscv: enable software resend of irqs MAINTAINERS: add RISC-V's patchwork Fangrui Song (1): riscv: Pass -mno-relax only on lld < 15.0.0 Greentime Hu (2): soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. riscv: Add cache information in AUX vector Heiko Stuebner (5): riscv: cleanup svpbmt cpufeature probing riscv: drop some idefs from CMO initialization riscv: use BIT() macros in t-head errata init riscv: use BIT() marco for cpufeature probing riscv: check for kernel config option in t-head memory types errata Jisheng Zhang (1): riscv: vdso: fix NULL deference in vdso_join_timens() when vfork Maciej W. Rozycki (1): RISC-V: Make port I/O string accessors actually work Palmer Dabbelt (9): doc: RISC-V: Document that misaligned accesses are supported Merge tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into for-next Merge patch series "Fix dt-validate issues on qemu dtbdumps due to dt-bindings" RISC-V: Avoid dereferening NULL regs in die() Merge patch series "Some style cleanups for recent extension additions" Merge patch series "Use composable cache instead of L2 cache" RISC-V: Re-enable counter access from userspace RISC-V: Make mmap() with PROT_WRITE imply PROT_READ RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output Shravan Chippa (1): dt-bindings: riscv: microchip: document the sev kit Vattipalli Praveen (1): riscv: dts: microchip: add sevkit device tree Wenting Zhang (1): riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb Zong Li (3): dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: define the macro for the register shifts .../interrupt-controller/sifive,plic-1.0.0.yaml | 5 + Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +- .../devicetree/bindings/riscv/microchip.yaml | 24 +- .../{sifive-l2-cache.yaml => sifive,ccache0.yaml} | 28 ++- .../devicetree/bindings/timer/sifive,clint.yaml | 18 +- Documentation/riscv/index.rst | 1 + Documentation/riscv/uabi.rst | 6 + MAINTAINERS | 4 +- arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 2 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 43 +++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 18 +- .../boot/dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 ++++ arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 179 +++++++++++++++ .../boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++ .../boot/dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++ arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 31 +-- arch/riscv/errata/thead/errata.c | 14 +- arch/riscv/include/asm/cacheflush.h | 2 + arch/riscv/include/asm/elf.h | 4 + arch/riscv/include/asm/io.h | 16 +- arch/riscv/include/asm/mmu.h | 1 - arch/riscv/include/uapi/asm/auxvec.h | 4 +- arch/riscv/kernel/cpu.c | 51 +++++ arch/riscv/kernel/cpufeature.c | 39 ++-- arch/riscv/kernel/setup.c | 4 +- arch/riscv/kernel/sys_riscv.c | 3 - arch/riscv/kernel/traps.c | 9 +- arch/riscv/kernel/vdso.c | 13 +- arch/riscv/mm/fault.c | 3 +- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 +- drivers/perf/riscv_pmu_sbi.c | 7 +- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- drivers/soc/sifive/sifive_ccache.c | 255 +++++++++++++++++++++ drivers/soc/sifive/sifive_l2_cache.c | 237 ------------------- include/soc/sifive/sifive_ccache.h | 16 ++ include/soc/sifive/sifive_l2_cache.h | 16 -- 41 files changed, 968 insertions(+), 379 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) create mode 100644 Documentation/riscv/uabi.rst create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts create mode 100644 drivers/soc/sifive/sifive_ccache.c delete mode 100644 drivers/soc/sifive/sifive_l2_cache.c create mode 100644 include/soc/sifive/sifive_ccache.h delete mode 100644 include/soc/sifive/sifive_l2_cache.h _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 21 Oct 2022 13:26:49 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv fixes for 6.1, take #1 Hi Paolo, We have two fixes for 6.1: 1) Fix for compile error seen when RISCV_ISA_ZICBOM is disabled. This fix touches code outside KVM RISC-V but I am including this here since it was affecting KVM compilation. 2) Fix for checking pending timer interrupt when RISC-V Sstc extension is available. Please pull. Regards, Anup The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780: Linux 6.1-rc1 (2022-10-16 15:36:24 -0700) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-fixes-6.1-1 for you to fetch changes up to cea8896bd936135559253e9b23340cfa1cdf0caf: RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for Sstc (2022-10-21 11:52:45 +0530) ---------------------------------------------------------------- KVM/riscv fixes for 6.1, take #1 - Fix compilation without RISCV_ISA_ZICBOM - Fix kvm_riscv_vcpu_timer_pending() for Sstc ---------------------------------------------------------------- Andrew Jones (1): RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel (1): RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for Sstc arch/riscv/include/asm/cacheflush.h | 8 ------- arch/riscv/include/asm/kvm_vcpu_timer.h | 1 + arch/riscv/kvm/vcpu.c | 3 +++ arch/riscv/kvm/vcpu_timer.c | 17 ++++++++++++-- arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 41 --------------------------------- 6 files changed, 57 insertions(+), 51 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Wed, 7 Dec 2022 16:03:28 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv changes for 6.2 Hi Paolo, We have the following KVM RISC-V changes for 6.2: 1) Allow unloading KVM module 2) Allow KVM user-space to set mvendorid, marchid, and mimpid 3) Several fixes and cleanups Please pull. Regards, Anup The following changes since commit 76dcd734eca23168cb008912c0f69ff408905235: Linux 6.1-rc8 (2022-12-04 14:48:12 -0800) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-6.2-1 for you to fetch changes up to 6ebbdecff6ae00557a52539287b681641f4f0d33: RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid (2022-12-07 09:17:49 +0530) ---------------------------------------------------------------- KVM/riscv changes for 6.2 - Allow unloading KVM module - Allow KVM user-space to set mvendorid, marchid, and mimpid - Several fixes and cleanups ---------------------------------------------------------------- Anup Patel (9): RISC-V: KVM: Exit run-loop immediately if xfer_to_guest fails RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config() RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h RISC-V: KVM: Remove redundant includes of asm/csr.h RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg() RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h RISC-V: Export sbi_get_mvendorid() and friends RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid Bo Liu (1): RISC-V: KVM: use vma_lookup() instead of find_vma_intersection() Christophe JAILLET (1): RISC-V: KVM: Simplify kvm_arch_prepare_memory_region() XiakaiPan (1): RISC-V: KVM: Add exit logic to main.c arch/riscv/include/asm/kvm_host.h | 16 +++---- arch/riscv/include/asm/kvm_vcpu_sbi.h | 6 +++ arch/riscv/include/uapi/asm/kvm.h | 3 ++ arch/riscv/kernel/sbi.c | 3 ++ arch/riscv/kvm/main.c | 6 +++ arch/riscv/kvm/mmu.c | 6 +-- arch/riscv/kvm/vcpu.c | 85 ++++++++++++++++++++++++++--------- arch/riscv/kvm/vcpu_sbi_base.c | 13 +++--- arch/riscv/kvm/vcpu_sbi_hsm.c | 1 - arch/riscv/kvm/vcpu_sbi_replace.c | 1 - arch/riscv/kvm/vcpu_sbi_v01.c | 1 - 11 files changed, 97 insertions(+), 44 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Wed, 28 Dec 2022 18:56:16 +0000 From: Conor Dooley To: palmer@dabbelt.com, linux-riscv@lists.infradead.org Subject: [GIT PULL] kconfig.socs symbol conversion --===============7728534401801400295== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="3x3z+Q1wAsImrJnV" Content-Disposition: inline --3x3z+Q1wAsImrJnV Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Palmer, Please pull part 1 of the Kconfig.socs cleanup work. This PR adds ARCH_FOO copies of SOC_FOO symbols, so that from v6.3 onwards I can convert the users of the old symbols to the new ones. I've also gone and converted the various bits of Kbuild infra over to the new symbols which I will merge into my dt-for-next branch, hence the PR. Part N will probably arrive this time next year, once an LTS has been released with the ARCH_FOO symbols in it. That seems like a fair way to make sure the ARCH_FOO symbols propagate to whatever out of tree defconfigs that exist. I've included the rest of my "RISC-V: kconfig.socs cleanup, part 1", series in this tag/PR as it depends on the earlier patches. I won't be merging those bits into my dt tree though as they're not needed there. Thanks, Conor. The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2: Linux 6.2-rc1 (2022-12-25 13:41:39 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/soc2arch-immutable for you to fetch changes up to 3af577f9826fdddefac42b35fc5eb3912c5b7d85: RISC-V: stop directly selecting drivers for SOC_CANAAN (2022-12-27 18:01:40 +0000) ---------------------------------------------------------------- SOC_FOO to ARCH_FOO conversion for RISC-V RISC-V is an outlier in using SOC_FOO rather than ARCH_FOO for vendors/micro-archs. SOC_FOO may make more sense (I personally prefer it), but the rest of the "world" uses ARCH_FOO. That'd be fine, with with an increasing number of existing SoC vendors moving to RISC-V, unifying our symbol names with the expectations of the rest of the world makes sense. Folks did not seem keen on changing the world (and they can't really be blamed for that) so convert RISC-V over to match. Add some ARCH_FOO stubs alongside the existing SOC_FOO ones, which will be removed once all users of SOC_FOO have been converted*, and convert the DT bits of RISC-V kbuild over to the new symbols. * It may be best to wait until after the next LTS to remove the SOC_FOO ones, for the sake of external users. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (6): RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO RISC-V: stop selecting the PolarFire SoC clock driver RISC-V: stop selecting SiFive clock and serial drivers directly RISC-V: stop directly selecting drivers for SOC_CANAAN arch/riscv/Kconfig.socs | 39 ++++++++++++++++++++++++++------------- arch/riscv/Makefile | 2 +- arch/riscv/boot/dts/Makefile | 2 +- arch/riscv/boot/dts/canaan/Makefile | 14 +++++++------- arch/riscv/boot/dts/microchip/Makefile | 8 ++++---- arch/riscv/boot/dts/sifive/Makefile | 4 ++-- arch/riscv/boot/dts/starfive/Makefile | 2 +- 7 files changed, 42 insertions(+), 29 deletions(-) --3x3z+Q1wAsImrJnV Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY6yRUAAKCRB4tDGHoIJi 0vFHAQC4NsE3f34JArygPgMGGaoh/+IqTnrMrCsvwZkMXDZdTQEA0x+Ys9WWy7rM DfJ+EusKadtcZ00d82Ka7xKjUQCVkwY= =Cw9W -----END PGP SIGNATURE----- --3x3z+Q1wAsImrJnV-- --===============7728534401801400295== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============7728534401801400295==-- . Date: Wed, 11 Jan 2023 21:35:27 +0000 From: Conor Dooley To: Arnd Bergmann Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com, conor@kernel.org, soc@kernel.org Subject: [GIT PULL] RISC-V DT for v6.2-rc4 --===============4102564517064402940== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="WK4zaOLL3DUE7zmA" Content-Disposition: inline --WK4zaOLL3DUE7zmA Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd! Been a quiet period since -rc1, so I only have a single DT fix for you. Figured I'd get it out of the way & write the script that I've been meaning to write since I sent the first pair of PRs at the same time. Hopefully I didn't break anything in the process! Thanks, Conor. The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2: Linux 6.2-rc1 (2022-12-25 13:41:39 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-fixes-for-v6.2-rc4 for you to fetch changes up to 43d5f5d63699724d47f0d9e0eae516a260d232b4: riscv: dts: sifive: fu740: fix size of pcie 32bit memory (2023-01-07 19:31:37 +0000) ---------------------------------------------------------------- RISC-V DeviceTrees for v6.2 SiFive: A solitary fix for the PCI memory regions on the unmatched, triggered by an SM768. No-one must have tried one until just recently! Signed-off-by: Conor Dooley ---------------------------------------------------------------- Ben Dooks (1): riscv: dts: sifive: fu740: fix size of pcie 32bit memory arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --WK4zaOLL3DUE7zmA Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY78rnwAKCRB4tDGHoIJi 0soeAQCLnAuzsdbNcFYcG40/VbWCdEVfeQY5EOJVHk73+ySWAQEAyUwtRDORVrxA OT5XeeMb5RwflnVfiJ5OFbRto4z7oAw= =KnuI -----END PGP SIGNATURE----- --WK4zaOLL3DUE7zmA-- --===============4102564517064402940== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4102564517064402940==-- . Date: Thu, 26 Jan 2023 18:57:38 +0000 From: Conor Dooley To: arnd@arndb.de Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org, soc@kernel.org Subject: [GIT PULL] RISC-V SoC drivers for v6.3 --===============3948905251306659732== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="61U62h1lCjSSIDqi" Content-Disposition: inline --61U62h1lCjSSIDqi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, I'm sending this one perhaps earlier than needed given there's going to be -rc8 this time around, just in case something about the PMU driver isn't to your liking. It'd be nice if there was a subsystem for these power management units as I wasn't sure if the API usage was correct. Heiko, who has experience from the rockchip driver, reviewed it, so I am happy with that. Thanks, Conor. The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2: Linux 6.2-rc1 (2022-12-25 13:41:39 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-for-v6.3-mw0 for you to fetch changes up to f3460326e38d6a084fb5b3348125a802567a3690: Merge patch series "JH7110 PMU Support" (2023-01-20 21:57:00 +0000) ---------------------------------------------------------------- RISC-V SoC drivers for v6.3-mw0 It's all StarFive stuff this time: Their new JH7110 SoC uses a SiFive core complex, and therefore a SiFive cache controller too. That needed a compatible added to both the binding and driver. The JH7110 also has power domains, which are supported by a new driver and a corresponding dt-binding. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (1): Merge patch series "JH7110 PMU Support" Emil Renner Berthing (2): dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC soc: sifive: ccache: Add StarFive JH7110 support Walker Chen (2): dt-bindings: power: Add starfive,jh7110-pmu soc: starfive: Add StarFive JH71XX pmu driver .../bindings/power/starfive,jh7110-pmu.yaml | 45 +++ .../devicetree/bindings/riscv/sifive,ccache0.yaml | 9 +- MAINTAINERS | 13 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 3 +- drivers/soc/sifive/Kconfig | 2 +- drivers/soc/starfive/Kconfig | 12 + drivers/soc/starfive/Makefile | 3 + drivers/soc/starfive/jh71xx_pmu.c | 383 +++++++++++++++++++++ include/dt-bindings/power/starfive,jh7110-pmu.h | 17 + 10 files changed, 485 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml create mode 100644 drivers/soc/starfive/Kconfig create mode 100644 drivers/soc/starfive/Makefile create mode 100644 drivers/soc/starfive/jh71xx_pmu.c create mode 100644 include/dt-bindings/power/starfive,jh7110-pmu.h --61U62h1lCjSSIDqi Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9LNIgAKCRB4tDGHoIJi 0oslAQDxpGfx6nGC6ll0OUrQ9NLZGo7e4AmoC34yaT+TZR5RhAD/VFycEClanwse mch60kBPEIgnQ8DM9OCXPVhc+GERpg4= =pwcV -----END PGP SIGNATURE----- --61U62h1lCjSSIDqi-- --===============3948905251306659732== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============3948905251306659732==-- . Date: Thu, 26 Jan 2023 19:09:45 +0000 From: Conor Dooley To: arnd@arndb.de Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org, soc@kernel.org Subject: [GIT PULL] RISC-V Devicetrees for v6.3 --===============8899100149448807918== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Dlm5AlAf3VZ5jgOb" Content-Disposition: inline --Dlm5AlAf3VZ5jgOb Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, DT stuff here for v6.3! I was kinda hoping to have a VisionFive 2 DT for you, but alas no. The changelog looks a bit odd since it's filled with un-reviewed commits of my own, but they went as a PR to Palmer & are in riscv's for-next too: https://lore.kernel.org/all/167225428483.14530.3368527680488639805.b4-ty@rivosinc.com/ They might also pop up as part of the Allwinner DT PR, if the D1 stuff lands for v6.3, which I hope does happen! Thanks, Conor. The following changes since commit 1b929c02afd37871d5afb9d498426f83432e71c2: Linux 6.2-rc1 (2022-12-25 13:41:39 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-for-v6.3-mw0 for you to fetch changes up to d9c36d016f6112e636f18a49a5f779c7f8667deb: Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM" (2023-01-25 11:09:32 +0000) ---------------------------------------------------------------- RISC-V Devicetrees for v6.3-mw0 Microchip: A vendor prefix for Aldec and both a binding and Devicetree for the Aldec TySoM devkit for PolarFire SoC. This Devicetree corresponds to what they are shipping in the SDK for rev2 boards. StarFive: Just the binding for the new StarFive JH7110 SoC and its first-party SDC the VisionFive 2. Other: I was expecting the Devicetree for the aforementioned board to be ready for this window, as the pinctrl driver had seem some review prior to v6.2 and both it & the base clock drivers are heavily based on the existing drivers for the JH7110. That didn't come to be.. Christmas, the RISC-V Summit in December and the Lunar New Year all playing a part perhaps. Because of that, both Palmer and I have the Kconfig.socs work in our branches, although in hindsight it probably wasn't needed here as I only added the TySoM Devicetree & the conflict would've been trivial. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (11): RISC-V: introduce ARCH_FOO kconfig aliases for SOC_FOO symbols RISC-V: kconfig.socs: convert usage of SOC_CANAAN to ARCH_CANAAN RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO RISC-V: stop selecting the PolarFire SoC clock driver RISC-V: stop selecting SiFive clock and serial drivers directly RISC-V: stop directly selecting drivers for SOC_CANAAN Merge tag 'soc2arch-immutable' into riscv-dt-for-next dt-bindings: vendor-prefixes: Add entry for Aldec dt-bindings: riscv: microchip: document the Aldec TySoM riscv: dts: microchip: add the Aldec TySoM's devicetree Merge patch series "Add a devicetree for the Aldec PolarFire SoC TySoM" Emil Renner Berthing (1): dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board .../devicetree/bindings/riscv/microchip.yaml | 1 + .../devicetree/bindings/riscv/starfive.yaml | 6 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + arch/riscv/Kconfig.socs | 39 +++-- arch/riscv/Makefile | 2 +- arch/riscv/boot/dts/Makefile | 2 +- arch/riscv/boot/dts/canaan/Makefile | 14 +- arch/riscv/boot/dts/microchip/Makefile | 9 +- .../boot/dts/microchip/mpfs-tysom-m-fabric.dtsi | 18 +++ arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 +++++++++++++++++++++ arch/riscv/boot/dts/sifive/Makefile | 4 +- arch/riscv/boot/dts/starfive/Makefile | 2 +- 12 files changed, 235 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts --Dlm5AlAf3VZ5jgOb Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9LP+QAKCRB4tDGHoIJi 0qSqAP9+VLU/tGX89ZeYWbEg7uuqMcN2rNt5KiRgFzmG7P3swAD/TRAvJPKuiV/c XSEhonnIeOZ3azZmPveEg2x2ULTxiQ4= =Tw66 -----END PGP SIGNATURE----- --Dlm5AlAf3VZ5jgOb-- --===============8899100149448807918== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============8899100149448807918==-- . Date: Tue, 7 Feb 2023 23:05:48 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , Andrew Jones , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv changes for 6.3 Hi Paolo, We have the following KVM RISC-V changes for 6.3: 1) Fix wrong usage of PGDIR_SIZE to check page sizes 2) Fix privilege mode setting in kvm_riscv_vcpu_trap_redirect() 3) Redirect illegal instruction traps to guest 4) SBI PMU support for guest Please pull. I will send another PR for 6.3 containing AIA CSR virtualization after Palmer has sent his first PR for 6.3 so that I can resolve conflicts with arch/riscv changes. I hope you are okay with this ?? Regards, Anup The following changes since commit 4ec5183ec48656cec489c49f989c508b68b518e3: Linux 6.2-rc7 (2023-02-05 13:13:28 -0800) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-6.3-1 for you to fetch changes up to c39cea6f38eefe356d64d0bc1e1f2267e282cdd3: RISC-V: KVM: Increment firmware pmu events (2023-02-07 20:36:08 +0530) ---------------------------------------------------------------- KVM/riscv changes for 6.3 - Fix wrong usage of PGDIR_SIZE to check page sizes - Fix privilege mode setting in kvm_riscv_vcpu_trap_redirect() - Redirect illegal instruction traps to guest - SBI PMU support for guest ---------------------------------------------------------------- Alexandre Ghiti (1): KVM: RISC-V: Fix wrong usage of PGDIR_SIZE to check page sizes Andy Chiu (1): RISC-V: KVM: Redirect illegal instruction traps to guest Anup Patel (1): RISC-V: KVM: Fix privilege mode setting in kvm_riscv_vcpu_trap_redirect() Atish Patra (14): perf: RISC-V: Define helper functions expose hpm counter width and count perf: RISC-V: Improve privilege mode filtering for perf RISC-V: Improve SBI PMU extension related definitions RISC-V: KVM: Define a probe function for SBI extension data structures RISC-V: KVM: Return correct code for hsm stop function RISC-V: KVM: Modify SBI extension handler to return SBI error code RISC-V: KVM: Add skeleton support for perf RISC-V: KVM: Add SBI PMU extension support RISC-V: KVM: Make PMU functionality depend on Sscofpmf RISC-V: KVM: Disable all hpmcounter access for VS/VU mode RISC-V: KVM: Implement trap & emulate for hpmcounters RISC-V: KVM: Implement perf support without sampling RISC-V: KVM: Support firmware events RISC-V: KVM: Increment firmware pmu events arch/riscv/include/asm/kvm_host.h | 4 + arch/riscv/include/asm/kvm_vcpu_pmu.h | 107 ++++++ arch/riscv/include/asm/kvm_vcpu_sbi.h | 13 +- arch/riscv/include/asm/sbi.h | 7 +- arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/main.c | 3 +- arch/riscv/kvm/mmu.c | 8 +- arch/riscv/kvm/tlb.c | 4 + arch/riscv/kvm/vcpu.c | 7 + arch/riscv/kvm/vcpu_exit.c | 9 + arch/riscv/kvm/vcpu_insn.c | 4 +- arch/riscv/kvm/vcpu_pmu.c | 633 ++++++++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu_sbi.c | 72 ++-- arch/riscv/kvm/vcpu_sbi_base.c | 27 +- arch/riscv/kvm/vcpu_sbi_hsm.c | 28 +- arch/riscv/kvm/vcpu_sbi_pmu.c | 86 +++++ arch/riscv/kvm/vcpu_sbi_replace.c | 50 +-- arch/riscv/kvm/vcpu_sbi_v01.c | 17 +- drivers/perf/riscv_pmu_sbi.c | 64 +++- include/linux/perf/riscv_pmu.h | 5 + 20 files changed, 1035 insertions(+), 114 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_pmu.h create mode 100644 arch/riscv/kvm/vcpu_pmu.c create mode 100644 arch/riscv/kvm/vcpu_sbi_pmu.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Fri, 17 Mar 2023 17:02:57 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Atish Patra , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv fixes for 6.3, take #1 Hi Paolo, We have one KVM RISC-V fix for 6.3: 1) Fix VM hang in case of timer delta being zero Please pull. Regards, Anup The following changes since commit eeac8ede17557680855031c6f305ece2378af326: Linux 6.3-rc2 (2023-03-12 16:36:44 -0700) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-fixes-6.3-1 for you to fetch changes up to 6eff38048944cadc3cddcf117acfa5199ec32490: riscv/kvm: Fix VM hang in case of timer delta being zero. (2023-03-17 13:32:54 +0530) ---------------------------------------------------------------- KVM/riscv fixes for 6.3, take #1 - Fix VM hang in case of timer delta being zero ---------------------------------------------------------------- Rajnesh Kanwal (1): riscv/kvm: Fix VM hang in case of timer delta being zero. arch/riscv/kvm/vcpu_timer.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Wed, 5 Apr 2023 17:05:01 +0100 From: Conor Dooley To: sboyd@kernel.org, p.zabel@pengutronix.de Cc: linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, hal.feng@starfivetech.com, emil.renner.berthing@canonical.com, conor@kernel.org, mturquette@baylibre.com Subject: [GIT PULL] Initial clk/reset support for JH7110 for v6.4 --===============7847576280501362496== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="VxiQgXSLDZ82ap6c" Content-Disposition: inline --VxiQgXSLDZ82ap6c Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Stephen, (and Philipp if you want I guess?), Here's a PR for the StarFive JH7110 clk/reset bits since I'd like to take the DT this cycle & depend on the binding headers. I've picked up R-B tags from Emil on all that patches, despite him being listed as an author, as things have changed quite a lot since he was involved in writing things many months ago. The base here is -rc2 rather than -rc1 as -rc1 has issues booting on this platform. Please pull and all that lark.. Cheers, Conor. The following changes since commit eeac8ede17557680855031c6f305ece2378af326: Linux 6.3-rc2 (2023-03-12 16:36:44 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-jh7110-clk-reset-for-6.4 for you to fetch changes up to 63a30e1f44d5e3afbb47efe8a15fd86feeb62b4b: MAINTAINERS: generalise StarFive clk/reset entries (2023-04-05 15:52:25 +0100) ---------------------------------------------------------------- Initial JH7110 clk/reset support A rake of patches, initially worked on by Emil & later picked up by Hal that add support for the sys/aon clock & reset controllers on StarFive's JH7110 SoC. This SoC is largely similar to the existing JH7100, so a bunch of refactoring is done to share as many bits as possible between the two. What's here (plus the already applied pinctrl bits) should be sufficient to boot a basic initramfs. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Emil Renner Berthing (13): dt-bindings: clock: Add StarFive JH7110 system clock and reset generator dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator clk: starfive: Factor out common JH7100 and JH7110 code clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h clk: starfive: Rename "jh7100" to "jh71x0" for the common code reset: Create subdirectory for StarFive drivers reset: starfive: Factor out common JH71X0 reset code reset: starfive: Extract the common JH71X0 reset code reset: starfive: Rename "jh7100" to "jh71x0" for the common code reset: starfive: jh71x0: Use 32bit I/O on 32bit registers clk: starfive: Add StarFive JH7110 system clock driver clk: starfive: Add StarFive JH7110 always-on clock driver MAINTAINERS: generalise StarFive clk/reset entries Hal Feng (3): clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE reset: starfive: Add StarFive JH7110 reset driver .../bindings/clock/starfive,jh7110-aoncrg.yaml | 107 +++ .../bindings/clock/starfive,jh7110-syscrg.yaml | 104 +++ MAINTAINERS | 22 +- drivers/clk/Makefile | 2 +- drivers/clk/starfive/Kconfig | 33 +- drivers/clk/starfive/Makefile | 6 +- drivers/clk/starfive/clk-starfive-jh7100-audio.c | 74 +-- drivers/clk/starfive/clk-starfive-jh7100.c | 716 ++++++--------------- drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---- drivers/clk/starfive/clk-starfive-jh7110-aon.c | 156 +++++ drivers/clk/starfive/clk-starfive-jh7110-sys.c | 490 ++++++++++++++ drivers/clk/starfive/clk-starfive-jh7110.h | 11 + drivers/clk/starfive/clk-starfive-jh71x0.c | 333 ++++++++++ drivers/clk/starfive/clk-starfive-jh71x0.h | 123 ++++ drivers/reset/Kconfig | 8 +- drivers/reset/Makefile | 2 +- drivers/reset/reset-starfive-jh7100.c | 173 ----- drivers/reset/starfive/Kconfig | 20 + drivers/reset/starfive/Makefile | 5 + drivers/reset/starfive/reset-starfive-jh7100.c | 74 +++ drivers/reset/starfive/reset-starfive-jh7110.c | 70 ++ drivers/reset/starfive/reset-starfive-jh71x0.c | 131 ++++ drivers/reset/starfive/reset-starfive-jh71x0.h | 14 + include/dt-bindings/clock/starfive,jh7110-crg.h | 221 +++++++ include/dt-bindings/reset/starfive,jh7110-crg.h | 154 +++++ 25 files changed, 2297 insertions(+), 864 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110.h create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h delete mode 100644 drivers/reset/reset-starfive-jh7100.c create mode 100644 drivers/reset/starfive/Kconfig create mode 100644 drivers/reset/starfive/Makefile create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h --VxiQgXSLDZ82ap6c Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZC2cLQAKCRB4tDGHoIJi 0lbzAQDfmv4s4TWUytYT+wpNfRfL91KsrUTqRM6RxNFhK728YgD9Ems0KgF/+RSI il/aq997LhB3O5joLUCnUUAkaHQy+ws= =rSdZ -----END PGP SIGNATURE----- --VxiQgXSLDZ82ap6c-- --===============7847576280501362496== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============7847576280501362496==-- . Date: Thu, 6 Apr 2023 18:36:56 +0100 From: Conor Dooley To: arnd@arndb.de Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org, soc@kernel.org Subject: [GIT PULL] RISC-V Devicetree fixes for v6.3-final --===============1371192995204712306== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Qet3MONiiEbbE/SP" Content-Disposition: inline --Qet3MONiiEbbE/SP Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Please pull a single fix, it's been a quiet window on the fixes front! I don't have any urgent fixes on the soc side either, only fixes for behaviour that cannot be triggered with an upstream kernel that I've put in for-next. Thanks, Conor. The following changes since commit fe15c26ee26efa11741a7b632e9f23b01aca4cc6: Linux 6.3-rc1 (2023-03-05 14:52:03 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-fixes-for-v6.3-final for you to fetch changes up to 8056dc043d7f74d7675d413cb3dc4fa290609922: riscv: dts: canaan: drop invalid spi-max-frequency (2023-03-26 23:58:27 +0100) ---------------------------------------------------------------- RISC-V Devicetree fixes for v6.3-final A solitary fix here from Krzysztof for an invalid property that should've probably been removed months ago, but was missed due to it being in a dtb that doesn't build w/ defconfig. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Krzysztof Kozlowski (1): riscv: dts: canaan: drop invalid spi-max-frequency arch/riscv/boot/dts/canaan/k210.dtsi | 1 - 1 file changed, 1 deletion(-) --Qet3MONiiEbbE/SP Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZC8DOAAKCRB4tDGHoIJi 0u3UAPwN7hF9kNXZBtGCINhx1e0Li3ok6JNeFQCv73oY1T3IAAEApFViwu9/4Jay LS0dKxYkk1FI6k7XEhNl9ozqycpIgwk= =h7tw -----END PGP SIGNATURE----- --Qet3MONiiEbbE/SP-- --===============1371192995204712306== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============1371192995204712306==-- . Date: Thu, 6 Apr 2023 21:11:23 +0100 From: Conor Dooley To: arnd@arndb.de Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org, soc@kernel.org Subject: [GIT PULL] RISC-V SoC drivers for v6.4 --===============3573548942076775370== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="MG9SQdyiof7sCpeZ" Content-Disposition: inline --MG9SQdyiof7sCpeZ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Please pull some updates for the "otherwise unloved" RISC-V SoC drivers for v6.4! The bulk of this is my fixing my own driver, and there's a fix in here to make sure that we don't hit randconfig build issues once !MMU is enabled for 32-bit kernels. Thanks, Conor. The following changes since commit fe15c26ee26efa11741a7b632e9f23b01aca4cc6: Linux 6.3-rc1 (2023-03-05 14:52:03 -0800) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-for-v6.4 for you to fetch changes up to 4dd472bdafcb660bea17bc63a97d06e24fcb36ed: soc: microchip: mpfs: add a prefix to rx_callback() (2023-04-03 20:32:43 +0100) ---------------------------------------------------------------- RISC-V SoC drivers for v6.4 Microchip: Mailbox controller & client changes for the system controller on PolarFire SoC. The controller bits have been acked by Jassi. Primarily the changes work around a "hardware" bug (really the system controller's software, but it may as well be hardware as customers cannot change it) where interrupts are not generated if a service fails. The mailbox controller driver is tweaked to use polling, rather than interrupt, mode and there are some changes to timeout code required in the client driver as a result. There's some opportunistic cleanup that I performed while doing the swap too. Canaan: A single fix for some randconfig issues that crop up when !mmu is enabled for 32-bit kernels, due to my changes in a previous release that swapped out select based entablement of the driver. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (10): mailbox: mpfs: fix an incorrect mask width mailbox: mpfs: switch to txdone_poll mailbox: mpfs: ditch a useless busy check mailbox: mpfs: check the service status in .tx_done() soc: microchip: mpfs: fix some horrible alignment soc: microchip: mpfs: use a consistent completion timeout soc: microchip: mpfs: simplify error handling in mpfs_blocking_transaction() soc: microchip: mpfs: handle timeouts and failed services differently Merge patch series "mailbox,soc: mpfs: add support for fallible services" soc: microchip: mpfs: add a prefix to rx_callback() Jesse Taube (1): soc: canaan: Make K210_SYSCTL depend on CLK_K210 drivers/mailbox/mailbox-mpfs.c | 55 +++++++++++++++------------- drivers/soc/canaan/Kconfig | 5 +-- drivers/soc/microchip/mpfs-sys-controller.c | 56 +++++++++++++++++++---------- 3 files changed, 72 insertions(+), 44 deletions(-) --MG9SQdyiof7sCpeZ Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZC8nawAKCRB4tDGHoIJi 0jpvAPsG/NvFHWbivVqaIaLXBOhx1O24bkBks+fD9Tjcj93OTAEAlfjInam2orOU RLfmeEtVNnF8u+KCbf4ioD2F1H6YOwA= =tcys -----END PGP SIGNATURE----- --MG9SQdyiof7sCpeZ-- --===============3573548942076775370== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============3573548942076775370==-- . Date: Thu, 6 Apr 2023 21:24:40 +0100 From: Conor Dooley To: arnd@arndb.de Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org, soc@kernel.org Subject: [GIT PULL] RISC-V Devicetrees for v6.4 --===============1247232526916017552== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0SfrAMaAlVV1aTTn" Content-Disposition: inline --0SfrAMaAlVV1aTTn Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hey Arnd, Please pull some Devicetree updates for v6.4, mainly adding the base level of support for the StarFive VisionFive v2. I wanted to get an initial PR out before -rc6, but I may have another PR adding some of the peripherals (pmu, mmc) for the StarFive stuff that are already reviewed etc, but need a rebase on top of what actually got applied. Is that okay, or will the end of next week be too late for you? As a note, this is against -rc2, rather than -rc1, as I wanted to apply the StarFive stuff to a branch there'd be a chance of it booting on for the sake of testing. Cheers, Conor. git request-pull complained that the tag was not present, but I checked my repo and it is there. =C2=AF\_(=E3=83=84)_/=C2=AF The following changes since commit eeac8ede17557680855031c6f305ece2378af326: Linux 6.3-rc2 (2023-03-12 16:36:44 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt= -for-v6.4 for you to fetch changes up to 4cd4beb98fe5ac2c4bcb995ba6e82322be174abb: Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-next (2023-04-0= 5 22:23:17 +0100) ---------------------------------------------------------------- RISC-V Devicetrees for v6.4 Microchip: A "fix" for the system controller's regs on PolarFire SoC, adding a missing reg property. The patch had been sitting there for months and I only re-found it recently, so you can guess how much of a "fix" it actually is. It'll become needed when the system controller's QSPI gets added in the future, but at present there's no urgency as the driver can handle both the current and "fixed" versions. StarFive: Basic support for the JH7110 & the associated first-party dev board, the VisionFive v2 (in two forms). There's a bunch of dt-bindings required for this too, all of which have had input from the DT folk. There's enough in this tag to boot to a console w/ an initramfs but little more. The SoC supports some of the "new" bit manipulation instructions, which is a good test for the recently added Zbb support in the kernel. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (3): riscv: dts: microchip: add mpfs specific macb reset support riscv: dts: microchip: fix the mpfs' mailbox regs Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-next Emil Renner Berthing (6): dt-bindings: clock: Add StarFive JH7110 system clock and reset genera= tor dt-bindings: clock: Add StarFive JH7110 always-on clock and reset gen= erator dt-bindings: timer: Add StarFive JH7110 clint dt-bindings: interrupt-controller: Add StarFive JH7110 plic riscv: dts: starfive: Add initial StarFive JH7110 device tree riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device t= ree Hal Feng (1): dt-bindings: riscv: Add SiFive S7 compatible Jianlong Huang (1): riscv: dts: starfive: Add StarFive JH7110 pin function definitions .../bindings/clock/starfive,jh7110-aoncrg.yaml | 107 +++++ .../bindings/clock/starfive,jh7110-syscrg.yaml | 104 +++++ .../interrupt-controller/sifive,plic-1.0.0.yaml | 1 + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + .../devicetree/bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 10 +- arch/riscv/boot/dts/starfive/Makefile | 6 +- arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 +++++++++++++ .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 + .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 + .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 215 +++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 500 +++++++++++++++++= ++++ include/dt-bindings/clock/starfive,jh7110-crg.h | 221 +++++++++ include/dt-bindings/reset/starfive,jh7110-crg.h | 154 +++++++ 14 files changed, 1650 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110= -aoncrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110= -syscrg.yaml create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive= -2-v1.2a.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive= -2-v1.3b.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive= -2.dtsi create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h --0SfrAMaAlVV1aTTn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZC8qiAAKCRB4tDGHoIJi 0qhcAQCM7InEIij/sPxm86jJxcCIC/GZwU78+cTUWy5qeRNq3AD+KL4NNY5BUpRD RxCDbFTkGVvy+EOe9zpEu48AGZaODQw= =pZyK -----END PGP SIGNATURE----- --0SfrAMaAlVV1aTTn-- --===============1247232526916017552== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============1247232526916017552==-- . Date: Fri, 21 Apr 2023 23:04:00 +0530 From: Anup Patel To: Paolo Bonzini Cc: Palmer Dabbelt , Palmer Dabbelt , Atish Patra , Atish Patra , Andrew Jones , KVM General , "open list:KERNEL VIRTUAL MACHINE FOR RISC-V (KVM/riscv)" , linux-riscv Subject: [GIT PULL] KVM/riscv changes for 6.4 Hi Paolo, We have the following KVM RISC-V changes for 6.4: 1) ONE_REG interface to enable/disable SBI extensions 2) Zbb extension for Guest/VM 3) AIA CSR virtualization 4) Few minor cleanups and fixes Please pull. Please note that the Zicboz series has been taken by Palmer through the RISC-V tree which results in few minor conflicts in the following files: arch/riscv/include/asm/hwcap.h arch/riscv/include/uapi/asm/kvm.h arch/riscv/kernel/cpu.c arch/riscv/kernel/cpufeature.c arch/riscv/kvm/vcpu.c I am not sure if a shared tag can make things easy for you or Palmer. Regards, Anup The following changes since commit 6a8f57ae2eb07ab39a6f0ccad60c760743051026: Linux 6.3-rc7 (2023-04-16 15:23:53 -0700) are available in the Git repository at: https://github.com/kvm-riscv/linux.git tags/kvm-riscv-6.4-1 for you to fetch changes up to 2f4d58f7635aec014428e73ef6120c4d0377c430: RISC-V: KVM: Virtualize per-HART AIA CSRs (2023-04-21 18:10:27 +0530) ---------------------------------------------------------------- KVM/riscv changes for 6.4 - ONE_REG interface to enable/disable SBI extensions - Zbb extension for Guest/VM - AIA CSR virtualization ---------------------------------------------------------------- Andrew Jones (1): RISC-V: KVM: Alphabetize selects Anup Patel (10): RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions RISC-V: KVM: Allow Zbb extension for Guest/VM RISC-V: Add AIA related CSR defines RISC-V: Detect AIA CSRs from ISA string RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines RISC-V: KVM: Initial skeletal support for AIA RISC-V: KVM: Implement subtype for CSR ONE_REG interface RISC-V: KVM: Add ONE_REG interface for AIA CSRs RISC-V: KVM: Use bitmap for irqs_pending and irqs_pending_mask RISC-V: KVM: Virtualize per-HART AIA CSRs David Matlack (1): KVM: RISC-V: Retry fault if vma_lookup() results become invalid arch/riscv/include/asm/csr.h | 107 +++++++++- arch/riscv/include/asm/hwcap.h | 8 + arch/riscv/include/asm/kvm_aia.h | 127 +++++++++++ arch/riscv/include/asm/kvm_host.h | 14 +- arch/riscv/include/asm/kvm_vcpu_sbi.h | 8 +- arch/riscv/include/uapi/asm/kvm.h | 51 ++++- arch/riscv/kernel/cpu.c | 2 + arch/riscv/kernel/cpufeature.c | 2 + arch/riscv/kvm/Kconfig | 10 +- arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/aia.c | 388 ++++++++++++++++++++++++++++++++++ arch/riscv/kvm/main.c | 22 +- arch/riscv/kvm/mmu.c | 28 ++- arch/riscv/kvm/vcpu.c | 194 +++++++++++++---- arch/riscv/kvm/vcpu_insn.c | 1 + arch/riscv/kvm/vcpu_sbi.c | 247 ++++++++++++++++++++-- arch/riscv/kvm/vcpu_sbi_base.c | 2 +- arch/riscv/kvm/vm.c | 4 + arch/riscv/kvm/vmid.c | 4 +- 19 files changed, 1129 insertions(+), 91 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_aia.h create mode 100644 arch/riscv/kvm/aia.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Mon, 12 Jun 2023 19:23:14 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, palmer@dabbelt.com, arnd@arndb.de, linux-riscv@lists.infradead.org, soc@kernel.org Subject: [GIT PULL] RISC-V Devicetrees for v6.5 --===============4180210389226876167== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="SPHo1XrUdCMqV28R" Content-Disposition: inline --SPHo1XrUdCMqV28R Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, A wee bunch of changes this time around as a bunch of the jh7110 stuff is still blocked on clock drivers. This'll probably be my only PR for the window, haven't got anything SoC-driver wise & it's unlikely that any of the other bits will be ready in the coming week. Thanks, Conor. The following changes since commit ac9a78681b921877518763ba0e89202254349d1b: Linux 6.4-rc1 (2023-05-07 13:34:35 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v6.5 for you to fetch changes up to e2c510d6d630fe6593a0cf87531913b4b08ebeb1: riscv: dts: starfive: Add cpu scaling for JH7110 SoC (2023-06-06 12:32:06 +0100) ---------------------------------------------------------------- RISC-V Devicetrees for v6.5 StarFive: Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P being power, support for the JH7110. PMIC and frequency scaling support for the JH7110 equipped VisionFive 2. Most of the DT bits for the JH7110, and the SBCs using it, are pending support for one of the clock controllers, so it's a smaller set of changes than I would have hoped for. Misc: Pick up some dt-binding cleanup that Palmer assigned to me & had no uptake from the respective maintainers. My powers of estimation failed me again, with part of my motivation for picking them up being the addition of new platforms that ended up not making it. Hopefully next window for those, as they were relatively close. Exclude the Allwinner and Renesas subdirectories from the Misc. MAINTAINERS entry, since I do not take care of those. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Conor Dooley (1): MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry Geert Uytterhoeven (2): dt-bindings: timer: sifive,clint: Clean up compatible value section dt-bindings: interrupt-controller: sifive,plic: Sort compatible values Mason Huo (2): riscv: dts: starfive: Enable axp15060 pmic for cpufreq riscv: dts: starfive: Add cpu scaling for JH7110 SoC Walker Chen (1): riscv: dts: starfive: Add PMU controller node Xingyu Wu (2): riscv: dts: starfive: jh7100: Add watchdog node riscv: dts: starfive: jh7110: Add watchdog node .../interrupt-controller/sifive,plic-1.0.0.yaml | 2 +- .../devicetree/bindings/timer/sifive,clint.yaml | 21 ++++----- MAINTAINERS | 2 + arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 +++++ .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 33 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 50 ++++++++++++++++++++++ 6 files changed, 104 insertions(+), 14 deletions(-) --SPHo1XrUdCMqV28R Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZIdikgAKCRB4tDGHoIJi 0kAsAP43klKSezOHEa+QjF/QQ1f1fyxvtAySDNTSsEgojKc4fwEApbFEslQl464M jxjezMJexYghxGs/PE8sYABSIHdfmwM= =pmTY -----END PGP SIGNATURE----- --SPHo1XrUdCMqV28R-- --===============4180210389226876167== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4180210389226876167==-- .