Date: Fri, 06 Sep 2024 09:21:30 -0700 (PDT) From: Palmer Dabbelt To: Linus Torvalds Subject: [GIT PULL] RISC-V Fixes for 6.11-rc7 The following changes since commit 32d5f7add080a936e28ab4142bfeea6b06999789: Merge patch series "RISC-V: hwprobe: Misaligned scalar perf fix and rename" (2024-08-15 13:12:21 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.11-rc7 for you to fetch changes up to 1ff95eb2bebda50c4c5406caaf201e0fcb24cc8f: riscv: Fix RISCV_ALTERNATIVE_EARLY (2024-09-03 07:57:55 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.11-rc7 * A revert for the mmap() change that ties the allocation range to the hint adress, as what we tried to do ended up regressing on other userspace workloads. * A fix to avoid a kernel memory leak when emulating misaligned accesses from userspace. * A Kconfig fix for toolchain vector detection, which now correctly detects vector support on toolchains where the V extension depends on the M extension. * A fix to avoid failing the linear mapping bootmem bounds check on NOMMU systems. * A fix for early alternatives on relocatable kernels. ---------------------------------------------------------------- That mmap() one is particuarly embarassing, as it didn't even fix the sv39 compatibility issue we set out to fix in the first place. We'll have a better fix for this, but I figured it would be best to get the revert out as it'll need to be backported and it breaks real workloads. ---------------------------------------------------------------- Alexandre Ghiti (2): riscv: Do not restrict memory size because of linear mapping on nommu riscv: Fix RISCV_ALTERNATIVE_EARLY Anton Blanchard (1): riscv: Fix toolchain vector detection Charlie Jenkins (3): Revert "RISC-V: mm: Document mmap changes" riscv: selftests: Remove mmap hint address checks riscv: mm: Do not restrict mmap address based on hint Palmer Dabbelt (1): Merge patch series "riscv: mm: Do not restrict mmap address based on hint" Samuel Holland (1): riscv: misaligned: Restrict user access to kernel memory Documentation/arch/riscv/vm-layout.rst | 16 ------ arch/riscv/Kconfig | 4 +- arch/riscv/include/asm/processor.h | 26 +-------- arch/riscv/include/asm/sbi.h | 20 ++++++- arch/riscv/kernel/Makefile | 6 ++- arch/riscv/kernel/sbi.c | 63 ---------------------- arch/riscv/kernel/sbi_ecall.c | 48 +++++++++++++++++ arch/riscv/kernel/traps_misaligned.c | 4 +- arch/riscv/mm/init.c | 2 +- tools/testing/selftests/riscv/mm/mmap_bottomup.c | 2 - tools/testing/selftests/riscv/mm/mmap_default.c | 2 - tools/testing/selftests/riscv/mm/mmap_test.h | 67 ------------------------ 12 files changed, 79 insertions(+), 181 deletions(-) create mode 100644 arch/riscv/kernel/sbi_ecall.c _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv . Date: Mon, 9 Sep 2024 15:33:36 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V soc fixes for v6.11-final --===============2423356840127917147== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="X44/jGdhTNky87+X" Content-Disposition: inline --X44/jGdhTNky87+X Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Here's the fix that was being discussed on IRC over the weekend. Cheers, conor. The following changes since commit 591940e22e287fb64ac07be275e343d860cb72d6: firmware: microchip: fix incorrect error report of programming:timeout on success (2024-08-22 20:47:16 +0100) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-fixes-for-v6.11-final for you to fetch changes up to 61f2e8a3a94175dbbaad6a54f381b2a505324610: riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz (2024-09-08 23:20:19 +0100) ---------------------------------------------------------------- RISC-V soc fixes for v6.11-final StarFive: A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz Signed-off-by: Conor Dooley ---------------------------------------------------------------- Xingyu Wu (1): riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) --X44/jGdhTNky87+X Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZt8HPwAKCRB4tDGHoIJi 0mq3AP9LdV4YzjeqnoHO1l4BBy42JMwqs9F3y6OSFv25I6GKwwD/ThjaBiaAPDIY M2Eqznog6Y5SphlJ4JiMzLyeGpx+YQA= =aYLb -----END PGP SIGNATURE----- --X44/jGdhTNky87+X-- --===============2423356840127917147== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============2423356840127917147==-- . Date: Tue, 10 Sep 2024 23:02:17 +0100 From: Conor Dooley To: soc@kernel.org Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V config for v6.12 --===============2535931206423146765== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="yP0QS5j1N9BokM1p" Content-Disposition: inline --yP0QS5j1N9BokM1p Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hey Arnd, Practically nothing for you this cycle, so this will be my only PR. There's both Microchip and Spacemit stuff on the lists, but none of it ready for this cycle. Cheers, Conor. The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-config-for-v6.12 for you to fetch changes up to 72160ec6cb12613663f26d89049b95f8dc9fa000: riscv: defconfig: Enable pinctrl support for CV18XX Series SoC (2024-09-09 12:55:53 +0100) ---------------------------------------------------------------- RISC-V config for v6.12 Two patches, enabling clock and pinctrl support in defconfig for Sopghgo devices. Signed-off-by: Conor Dooley ---------------------------------------------------------------- Chen Wang (1): riscv: defconfig: sophgo: enable clks for sg2042 Inochi Amaoto (1): riscv: defconfig: Enable pinctrl support for CV18XX Series SoC arch/riscv/configs/defconfig | 7 +++++++ 1 file changed, 7 insertions(+) --yP0QS5j1N9BokM1p Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZuDB6QAKCRB4tDGHoIJi 0hNXAP0YwgjXERXateyyMSzrmh3Ax84qnZUGVW/ofoKk2cVTLAEAx6V6QwqDSvuW ELWvPRfyrTazD2XyC/ukrX05gjbSsQw= =0yyF -----END PGP SIGNATURE----- --yP0QS5j1N9BokM1p-- --===============2535931206423146765== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============2535931206423146765==-- .