Subject: [PATCH] bcachefs: Fix NULL pointer dereference in bch2_opt_to_text From: Mohammed Anees To: Kent Overstreet Cc: linux-bcachefs@vger.kernel.org, linux-kernel@vger.kernel.org, Mohammed Anees , syzbot+37186860aa7812b331d5@syzkaller.appspotmail.com Date: Mon, 16 Sep 2024 21:03:10 +0000 . Subject: [syzbot] [usb?] KASAN: slab-use-after-free Read in raw_process_ep_io From: syzbot To: andreyknvl@gmail.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, syzkaller-bugs@googlegroups.com Date: Mon, 16 Sep 2024 14:10:32 -0700 . Subject: [PATCH v6 0/3] rust: Add irq abstraction, SpinLockIrq From: Lyude Paul To: rust-for-linux@vger.kernel.org Cc: Danilo Krummrich , airlied@redhat.com, Ingo Molnar , Will Deacon , Waiman Long , Peter Zijlstra , Thomas Gleixner , linux-kernel@vger.kernel.org, Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Date: Mon, 16 Sep 2024 17:28:03 -0400 . Subject: [PATCH v2 0/3] Add clock controller support for Spacemit K1 From: Haylen Chu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Inochi Amaoto , Chen Wang , Jisheng Zhang , Haylen Chu Date: Mon, 16 Sep 2024 22:20:57 +0000 . Subject: [PATCH 0/1] RISC-V: Fix building rust when using GCC toolchain From: Jason Montleon To: ojeda@kernel.org, alex.gaynor@gmail.com, boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@kernel.org, aliceryhl@google.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, nathan@kernel.org, ndesaulniers@google.com, morbo@google.com, justinstitt@google.com Cc: rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, llvm@lists.linux.dev, Jason Montleon Date: Mon, 16 Sep 2024 20:08:47 -0400 . Subject: [RFC] riscv/entry: issue about a0/orig_a0 register and ENOSYS From: Celeste Liu To: linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Oleg Nesterov , "Dmitry V. Levin" Cc: Andrea Bolognani , WANG Xuerui , Jiaxun Yang , Huacai Chen , Felix Yan , Ruizhe Pan , Shiqi Zhang , Guo Ren , Yao Zi , Yangyu Chen , Han Gao , linux-kernel@vger.kernel.org, rsworktech@outlook.com Date: Tue, 17 Sep 2024 12:09:15 +0800 . Subject: [PATCH v5] cxl/region: Fix wrong logic for finding a free switch cxl decoder From: Zijun Hu To: Greg Kroah-Hartman , Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams Cc: Zijun Hu , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, Zijun Hu Date: Tue, 17 Sep 2024 07:27:49 +0800 . Subject: [PATCH v2] Docs/zh_CN: Translate page_tables.rst to Simplified Chinese From: Pengyu Zhang To: alexs@kernel.org, siyanteng@loongson.cn, corbet@lwn.net, seakeel@gmail.com, si.yanteng@linux.dev Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, zpenya1314@gmail.com, yaxin_wang_uestc@163.com Date: Tue, 17 Sep 2024 11:22:41 +0800 . Subject: [PATCH 0/1] rust: sync: Add Lock::from_raw for ZST data types From: Lyude Paul To: rust-for-linux@vger.kernel.org Cc: Danilo Krummrich , airlied@redhat.com, Ingo Molnar , Will Deacon , Waiman Long , Peter Zijlstra , Thomas Gleixner , linux-kernel@vger.kernel.org, Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Date: Mon, 16 Sep 2024 18:05:45 -0400 . Subject: [PATCH] x86/ftrace: Include From: Sami Tolvanen To: Steven Rostedt , Masami Hiramatsu , Mark Rutland , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: Sami Tolvanen , Masahiro Yamada , linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org Date: Mon, 16 Sep 2024 22:15:57 +0000 . Subject: [PATCH] usb: gadget: r8a66597-udc: Fix double free in r8a66597_probe From: Mikhail Arkhipov To: Greg Kroah-Hartman Cc: Mikhail Arkhipov , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Felipe Balbi , Ben Dooks , Sebastian Andrzej Siewior , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org Date: Tue, 17 Sep 2024 01:29:37 +0300 . Subject: [PATCH v2] usb: dwc3: core: Stop processing of pending events if controller is halted From: Selvarasu Ganesan To: Thinh.Nguyen@synopsys.com, gregkh@linuxfoundation.org, felipe.balbi@linux.intel.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jh0801.jung@samsung.com, dh10.jung@samsung.com, naushad@samsung.com, akash.m5@samsung.com, rc93.raju@samsung.com, taehyun.cho@samsung.com, hongpooh.kim@samsung.com, eomji.oh@samsung.com, shijie.cai@samsung.com, Selvarasu Ganesan , stable Date: Tue, 17 Sep 2024 04:15:41 +0530 . Subject: [PATCH] bcachefs: add GFP_ZERO flag in btree_bounce_alloc From: Piotr Zalewski To: kent.overstreet@linux.dev, linux-bcachefs@vger.kernel.org, linux-kernel@vger.kernel.org Cc: skhan@linuxfoundation.org, Piotr Zalewski Date: Mon, 16 Sep 2024 22:47:57 +0000 . Subject: [PATCH 00/19] kthread: Introduce preferred affinity v3 From: Frederic Weisbecker To: LKML Cc: Frederic Weisbecker , Andrew Morton , Peter Zijlstra , Thomas Gleixner , Vlastimil Babka Date: Tue, 17 Sep 2024 00:49:04 +0200 . Subject: [PATCH v2] drm/panic: Fix uninitialized spinlock acquisition with CONFIG_DRM_PANIC=n From: Lyude Paul To: dri-devel@lists.freedesktop.org Cc: Daniel Vetter , stable@vger.kernel.org, Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jocelyn Falempe , linux-kernel@vger.kernel.org (open list) Date: Mon, 16 Sep 2024 19:00:08 -0400 . Subject: [PATCH v3] fs/exfat: resolve memory leak from exfat_create_upcase_table() From: Daniel Yang To: viro@zeniv.linux.org.uk, Namjae Jeon , Sungjong Seo , linux-fsdevel@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Daniel Yang , syzbot+e1c69cadec0f1a078e3d@syzkaller.appspotmail.com Date: Mon, 16 Sep 2024 16:05:06 -0700 . Subject: [PATCH v2 0/1] rust: sync: Add Lock::from_raw for Lock<(), B> From: Lyude Paul To: rust-for-linux@vger.kernel.org Cc: Danilo Krummrich , airlied@redhat.com, Ingo Molnar , Will Deacon , Waiman Long , Peter Zijlstra , Thomas Gleixner , linux-kernel@vger.kernel.org, Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Date: Mon, 16 Sep 2024 19:17:30 -0400 . Subject: [PATCH v3] usb: dwc3: core: Stop processing of pending events if controller is halted From: Selvarasu Ganesan To: Thinh.Nguyen@synopsys.com, gregkh@linuxfoundation.org, felipe.balbi@linux.intel.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jh0801.jung@samsung.com, dh10.jung@samsung.com, naushad@samsung.com, akash.m5@samsung.com, rc93.raju@samsung.com, taehyun.cho@samsung.com, hongpooh.kim@samsung.com, eomji.oh@samsung.com, shijie.cai@samsung.com, Selvarasu Ganesan , stable@kernel.org Date: Tue, 17 Sep 2024 04:48:09 +0530 . Subject: linux-next: manual merge of the mm tree with Linus' tree From: Stephen Rothwell To: Andrew Morton Cc: Linux Kernel Mailing List , Linux Next Mailing List , Oleg Nesterov , "Peter Zijlstra (Intel)" , Sven Schnelle Date: Tue, 17 Sep 2024 09:27:39 +1000 . Subject: [PATCH] rust: Adds examples for the `Either` type From: Nell Shamrell-Harrington To: ojeda@kernel.org, alex.gaynor@gmail.com, wedsonaf@gmail.com Cc: boqun.feng@gmail.com, gary@garyguo.net, bjorn3_gh@protonmail.com, benno.lossin@proton.me, a.hindborg@samsung.com, aliceryhl@google.com, tmgross@umich.edu, linux@obei.io, kernel@valentinobst.de, kent.overstreet@gmail.com, matthew.d.roper@intel.com, kartikprajapati987@gmail.com, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 16 Sep 2024 23:35:07 +0000 . Subject: [GIT PULL] nolibc for 6.12-rc1 From: Shuah Khan To: Linus Torvalds Cc: shuah , Shuah Khan , =?UTF-8?Q?Thomas_Wei=C3=9Fschuh?= , Willy Tarreau , "Paul E. McKenney" , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 16 Sep 2024 17:37:52 -0600 This is a multi-part message in MIME format. --------------ZQ3Vjn9X99yKUfzxIDogQqJT Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Linus, Please pull the following nolibc update for Linux 6.12-rc1. This nolibc update for Linux 6.12-rc1 consists of: Highlights ---------- * Clang support (including LTO) Other Changes ------------- * stdbool.h support * argc/argv/envp arguments for constructors * Small #include ordering fix Test Results: Passed: tools/testing/selftests/nolibc/run-tests.sh tools/testing/selftests/nolibc/run-tests.sh -m user diff is attached. thanks, -- Shuah ---------------------------------------------------------------- The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest tags/linux_kselftest-nolibc-6.12-rc1 for you to fetch changes up to 248f6b935bbd8f7bc211cce2b6fd76be4c449848: Merge tag 'nolibc-20240824-for-6.12-1' of https://git.kernel.org/pub/scm/linux/kernel/git/nolibc/linux-nolibc into nolibc (2024-08-27 06:43:34 -0600) ---------------------------------------------------------------- linux_kselftest-nolibc-6.12-rc1 This nolibc update for Linux 6.12-rc1 consists of: Highlights ---------- * Clang support (including LTO) Other Changes ------------- * stdbool.h support * argc/argv/envp arguments for constructors * Small #include ordering fix ---------------------------------------------------------------- Shuah Khan (1): Merge tag 'nolibc-20240824-for-6.12-1' of https://git.kernel.org/pub/scm/linux/kernel/git/nolibc/linux-nolibc into nolibc Thomas Weißschuh (21): tools/nolibc: include arch.h from string.h tools/nolibc: add stdbool.h header tools/nolibc: pass argc, argv and envp to constructors tools/nolibc: arm: use clang-compatible asm syntax tools/nolibc: mips: load current function to $t9 tools/nolibc: powerpc: limit stack-protector workaround to GCC tools/nolibc: compiler: introduce __nolibc_has_attribute() tools/nolibc: move entrypoint specifics to compiler.h tools/nolibc: compiler: use attribute((naked)) if available selftests/nolibc: report failure if no testcase passed selftests/nolibc: avoid passing NULL to printf("%s") selftests/nolibc: determine $(srctree) first selftests/nolibc: add support for LLVM= parameter selftests/nolibc: add cc-option compatible with clang cross builds selftests/nolibc: run-tests.sh: avoid overwriting CFLAGS_EXTRA selftests/nolibc: don't use libgcc when building with clang selftests/nolibc: use correct clang target for s390/systemz selftests/nolibc: run-tests.sh: allow building through LLVM tools/nolibc: crt: mark _start_c() as used tools/nolibc: stackprotector: mark implicitly used symbols as used tools/nolibc: x86_64: use local label in memcpy/memmove tools/include/nolibc/Makefile | 1 + tools/include/nolibc/arch-aarch64.h | 4 +-- tools/include/nolibc/arch-arm.h | 8 +++--- tools/include/nolibc/arch-i386.h | 4 +-- tools/include/nolibc/arch-loongarch.h | 4 +-- tools/include/nolibc/arch-mips.h | 8 ++++-- tools/include/nolibc/arch-powerpc.h | 6 ++-- tools/include/nolibc/arch-riscv.h | 4 +-- tools/include/nolibc/arch-s390.h | 4 +-- tools/include/nolibc/arch-x86_64.h | 8 +++--- tools/include/nolibc/compiler.h | 24 +++++++++++----- tools/include/nolibc/crt.h | 25 +++++++++-------- tools/include/nolibc/nolibc.h | 3 +- tools/include/nolibc/stackprotector.h | 4 +-- tools/include/nolibc/stdbool.h | 16 +++++++++++ tools/include/nolibc/string.h | 1 + tools/testing/selftests/nolibc/Makefile | 41 +++++++++++++++++++--------- tools/testing/selftests/nolibc/nolibc-test.c | 9 +++--- tools/testing/selftests/nolibc/run-tests.sh | 16 ++++++++--- 19 files changed, 123 insertions(+), 67 deletions(-) create mode 100644 tools/include/nolibc/stdbool.h ---------------------------------------------------------------- --------------ZQ3Vjn9X99yKUfzxIDogQqJT Content-Type: text/x-patch; charset=UTF-8; name="linux_kselftest-nolibc-6.12-rc1.diff" Content-Disposition: attachment; filename="linux_kselftest-nolibc-6.12-rc1.diff" Content-Transfer-Encoding: base64 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Subject: [GIT PULL] Kselftest update for Linux 6.12-rc1 From: Shuah Khan To: Linus Torvalds Cc: shuah , Shuah Khan , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 16 Sep 2024 18:13:16 -0600 This is a multi-part message in MIME format. --------------CreUzoFYiIuW8Ze14BFG3Ot7 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Linus, Please pull the following kselftest next update for Linux 6.12-rc1. This kselftest update for Linux 6.12-rc1 consists of: -- test coverage for dup_fd() failure handling in unshare_fd() -- new selftest for the acct() syscall -- basic uprobe testcase -- several small fixes and cleanups to existing tests -- user and strscpy removal as they became kunit tests -- fixes to build failures and warnings diff is attached. thanks, -- Shuah ---------------------------------------------------------------- The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest tags/linux_kselftest-next-6.12-rc1 for you to fetch changes up to a0474b8d5974e142461ac7584c996feea167bcc1: selftests: kselftest: Use strerror() on nolibc (2024-09-11 09:52:33 -0600) ---------------------------------------------------------------- linux_kselftest-next-6.12-rc1 This kselftest update for Linux 6.12-rc1 consists of: -- test coverage for dup_fd() failure handling in unshare_fd() -- new selftest for the acct() syscall -- basic uprobe testcase -- several small fixes and cleanups to existing tests -- user and strscpy removal as they became kunit tests -- fixes to build failures and warnings ---------------------------------------------------------------- Abdulrasaq Lawani (1): selftest: acct: Add selftest for the acct() syscall Abhinav Jain (1): selftests: filesystems: fix warn_unused_result build warnings Al Viro (1): selftests:core: test coverage for dup_fd() failure handling in unshare_fd() Anders Roxell (2): selftests: rust: config: add trailing newline selftests: rust: config: disable GCC_PLUGINS Chang Yu (1): selftests/exec: Fix grammar in an error message. Masahiro Yamada (2): selftests: harness: remove unneeded __constructor_order_last() selftests: harness: rename __constructor_order for clarification Masami Hiramatsu (Google) (3): selftests/uprobes: Add a basic uprobe testcase selftests/ftrace: Add required dependency for kprobe tests selftests/ftrace: Fix eventfs ownership testcase to find mount point Muhammad Usama Anjum (3): selftests: tpm2: redirect python unittest logs to stdout selftests: user: remove user suite selftests: lib: remove strscpy test Piotr Zalewski (1): kselftest: timers: Fix const correctness Shreeya Patel (1): kselftest: cpufreq: Add RTC wakeup alarm Shuah Khan (1): selftests:resctrl: Fix build failure on archs without __cpuid_count() Steven Rostedt (Google) (2): tracing/selftests: Run the ownership test twice selftests/ftrace: Fix test to handle both old and new kernels zhang jiao (2): selftests/timers: Remove unused NSEC_PER_SEC macro selftests: kselftest: Use strerror() on nolibc tools/testing/selftests/Makefile | 2 +- tools/testing/selftests/acct/.gitignore | 3 + tools/testing/selftests/acct/Makefile | 5 ++ tools/testing/selftests/acct/acct_syscall.c | 78 ++++++++++++++++++ tools/testing/selftests/core/Makefile | 2 +- tools/testing/selftests/core/unshare_test.c | 94 ++++++++++++++++++++++ tools/testing/selftests/cpufreq/cpufreq.sh | 15 ++++ tools/testing/selftests/cpufreq/main.sh | 13 ++- .../drivers/s390x/uvdevice/test_uvdevice.c | 6 -- tools/testing/selftests/exec/execveat.c | 2 +- .../filesystems/statmount/statmount_test_ns.c | 7 +- .../ftrace/test.d/00basic/test_ownership.tc | 46 +++++++---- .../ftrace/test.d/dynevent/add_remove_uprobe.tc | 26 ++++++ .../ftrace/test.d/ftrace/func_set_ftrace_file.tc | 9 ++- .../ftrace/test.d/kprobe/kprobe_args_char.tc | 2 +- .../ftrace/test.d/kprobe/kprobe_args_string.tc | 2 +- tools/testing/selftests/hid/hid_bpf.c | 6 -- tools/testing/selftests/kselftest.h | 10 +-- tools/testing/selftests/kselftest_harness.h | 18 +---- tools/testing/selftests/lib/Makefile | 3 +- tools/testing/selftests/lib/config | 1 - tools/testing/selftests/lib/strscpy.sh | 3 - tools/testing/selftests/resctrl/cat_test.c | 7 +- tools/testing/selftests/rtc/rtctest.c | 7 -- tools/testing/selftests/rust/config | 3 +- tools/testing/selftests/timers/change_skew.c | 3 - tools/testing/selftests/timers/skew_consistency.c | 2 - tools/testing/selftests/timers/threadtest.c | 4 +- tools/testing/selftests/tpm2/test_async.sh | 2 +- tools/testing/selftests/tpm2/test_smoke.sh | 2 +- tools/testing/selftests/tpm2/test_space.sh | 2 +- tools/testing/selftests/user/Makefile | 9 --- tools/testing/selftests/user/config | 1 - tools/testing/selftests/user/test_user_copy.sh | 18 ----- 34 files changed, 302 insertions(+), 111 deletions(-) create mode 100644 tools/testing/selftests/acct/.gitignore create mode 100644 tools/testing/selftests/acct/Makefile create mode 100644 tools/testing/selftests/acct/acct_syscall.c create mode 100644 tools/testing/selftests/core/unshare_test.c create mode 100644 tools/testing/selftests/ftrace/test.d/dynevent/add_remove_uprobe.tc delete mode 100755 tools/testing/selftests/lib/strscpy.sh delete mode 100644 tools/testing/selftests/user/Makefile delete mode 100644 tools/testing/selftests/user/config delete mode 100755 tools/testing/selftests/user/test_user_copy.sh ---------------------------------------------------------------- --------------CreUzoFYiIuW8Ze14BFG3Ot7 Content-Type: text/x-patch; charset=UTF-8; name="linux_kselftest-next-6.12-rc1.diff" Content-Disposition: attachment; filename="linux_kselftest-next-6.12-rc1.diff" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL3Rvb2xzL3Rlc3Rpbmcvc2VsZnRlc3RzL01ha2VmaWxlIGIvdG9vbHMv dGVzdGluZy9zZWxmdGVzdHMvTWFrZWZpbGUKaW5kZXggYmM4ZmU5ZThmN2YyLi5mNTFmY2Nl YjQ1ZmQgMTAwNjQ0Ci0tLSBhL3Rvb2xzL3Rlc3Rpbmcvc2VsZnRlc3RzL01ha2VmaWxlCisr KyBiL3Rvb2xzL3Rlc3Rpbmcvc2VsZnRlc3RzL01ha2VmaWxlCkBAIC0xLDQgKzEsNSBAQAog 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Subject: arch/powerpc/kernel/trace/ftrace.c:752:46: sparse: sparse: cast truncates bits from constant value (200000000 becomes 0) From: kernel test robot To: Naveen N Rao Cc: oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Ellerman , Christophe Leroy Date: Tue, 17 Sep 2024 08:13:48 +0800 . Subject: [syzbot] [usb?] WARNING: refcount bug in get_taint (2) From: syzbot To: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, rafael@kernel.org, syzkaller-bugs@googlegroups.com Date: Mon, 16 Sep 2024 17:15:20 -0700 . Subject: [GIT PULL] Hyper-V next for v6.12 From: Wei Liu To: Linus Torvalds Cc: Wei Liu , Linux on Hyper-V List , Linux Kernel List , kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com Date: Tue, 17 Sep 2024 00:38:37 +0000 Hi Linus, The following changes since commit 47ac09b91befbb6a235ab620c32af719f8208399: Linux 6.11-rc4 (2024-08-18 13:17:27 -0700) are available in the Git repository at: ssh://git@gitolite.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git tags/hyperv-next-signed-20240916 for you to fetch changes up to 94e86b174d103d941b4afc4f016af8af9e5352fa: tools/hv: Add memory allocation check in hv_fcopy_start (2024-09-09 01:09:27 +0000) ---------------------------------------------------------------- hyperv-next for v6.12 - Optimize boot time by concurrent execution of hv_synic_init() (Saurabh Sengar) - Use helpers to read control registers in hv_snp_boot_ap() (Yosry Ahmed) - Add memory allocation check in hv_fcopy_start (Zhu Jun) ---------------------------------------------------------------- Saurabh Sengar (1): Drivers: hv: vmbus: Optimize boot time by concurrent execution of hv_synic_init() Yosry Ahmed (1): x86/hyperv: use helpers to read control registers in hv_snp_boot_ap() Zhu Jun (1): tools/hv: Add memory allocation check in hv_fcopy_start arch/x86/hyperv/ivm.c | 6 +++--- drivers/hv/vmbus_drv.c | 34 +++++++++++++++++++++++++++++++--- tools/hv/hv_fcopy_uio_daemon.c | 7 +++++++ 3 files changed, 41 insertions(+), 6 deletions(-) . Subject: [PATCH v3 0/1] Add KUnit tests for llist From: Artur Alves To: Andrew Morton , linux-kernel@vger.kernel.org, Brendan Higgins , David Gow , Rae Moar , linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com Cc: n@nfraprado.net, andrealmeid@riseup.net, vinicius@nukelet.com, diego.daniel.professional@gmail.com Date: Mon, 16 Sep 2024 21:51:15 -0300 . Subject: [PATCH v1] objtool: Also include tools/include/uapi From: HONG Yifan To: Josh Poimboeuf , Peter Zijlstra Cc: HONG Yifan , kernel-team@android.com, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 01:28:08 +0000 . Subject: [GIT PULL] KUnit update for Linux 6.12-rc1 From: Shuah Khan To: Linus Torvalds Cc: shuah , Shuah Khan , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, David Gow , Brendan Higgins Date: Mon, 16 Sep 2024 19:43:05 -0600 This is a multi-part message in MIME format. --------------lDmTx2uXH530aimSr6U5KQT6 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Linus, Please pull the following kunit update for Linux 6.12-rc1. This kunit update for Linux 6.12-rc1 consists of: -- a new int_pow test suite -- documentation update to clarify filename best practices -- kernel-doc fix for EXPORT_SYMBOL_IF_KUNIT -- change to build compile_commands.json automatically instead of requiring a manual build. diff is attached. thanks, -- Shuah ---------------------------------------------------------------- The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest tags/linux_kselftest-kunit-6.12-rc1 for you to fetch changes up to 7fcc9b53216cd87f73cc6dbb404220350ddc93b8: lib/math: Add int_pow test suite (2024-09-12 10:03:00 -0600) ---------------------------------------------------------------- linux_kselftest-kunit-6.12-rc1 This kunit update for Linux 6.12-rc1 consists of: -- a new int_pow test suite -- documentation update to clarify filename best practices -- kernel-doc fix for EXPORT_SYMBOL_IF_KUNIT -- change to build compile_commands.json automatically instead of requiring a manual build. ---------------------------------------------------------------- Brendan Jackman (1): kunit: tool: Build compile_commands.json Kees Cook (1): Documentation: KUnit: Update filename best practices Luis Felipe Hernandez (1): lib/math: Add int_pow test suite Michal Wajdeczko (1): kunit: Fix kernel-doc for EXPORT_SYMBOL_IF_KUNIT Documentation/dev-tools/kunit/style.rst | 29 ++++++++++++------ include/kunit/visibility.h | 1 + lib/Kconfig.debug | 16 ++++++++++ lib/math/Makefile | 1 + lib/math/tests/Makefile | 3 ++ lib/math/tests/int_pow_kunit.c | 52 +++++++++++++++++++++++++++++++++ tools/testing/kunit/kunit_kernel.py | 3 +- 7 files changed, 95 insertions(+), 10 deletions(-) create mode 100644 lib/math/tests/Makefile create mode 100644 lib/math/tests/int_pow_kunit.c ---------------------------------------------------------------- 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Subject: arch/powerpc/platforms/44x/uic.c:40:12: sparse: sparse: symbol 'primary_uic' was not declared. Should it be static? From: kernel test robot To: Christophe Leroy Cc: oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Michael Ellerman Date: Tue, 17 Sep 2024 09:48:51 +0800 . Subject: [PATCH net-next v5] net: qcom/emac: Find sgmii_ops by device_for_each_child() From: Zijun Hu To: Timur Tabi , "David S. Miller" , Greg Kroah-Hartman , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Zijun Hu , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Zijun Hu Date: Tue, 17 Sep 2024 09:57:33 +0800 . Subject: include/linux/ftrace.h:138:9: error: call to undeclared function 'arch_ftrace_get_regs'; ISO C99 and later do not support implicit function declarations From: kernel test robot To: Puranjay Mohan Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Palmer Dabbelt , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= Date: Tue, 17 Sep 2024 09:59:19 +0800 . Subject: [PATCHv5 0/7] zram: optimal post-processing target selection From: Sergey Senozhatsky To: Andrew Morton , Minchan Kim Cc: linux-kernel@vger.kernel.org, Sergey Senozhatsky Date: Tue, 17 Sep 2024 11:09:05 +0900 . Subject: [PATCH] binder: use augmented rb-tree for faster descriptor lookup From: Shu Han To: gregkh@linuxfoundation.org, arve@android.com, tkjos@android.com, maco@android.com, joel@joelfernandes.org, brauner@kernel.org, cmllamas@google.com, surenb@google.com Cc: linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 11:02:03 +0800 . Subject: linux-next: duplicate patch in the watchdog tree From: Stephen Rothwell To: Wim Van Sebroeck , Olof Johansson , Arnd Bergmann Cc: ARM , Linux Kernel Mailing List , Linux Next Mailing List Date: Tue, 17 Sep 2024 13:03:25 +1000 . Subject: linux-next: duplicate patch in the workqueues tree From: Stephen Rothwell To: Tejun Heo , Andrew Morton Cc: Linux Kernel Mailing List , Linux Next Mailing List Date: Tue, 17 Sep 2024 13:42:52 +1000 . Subject: drivers/cpufreq/s3c64xx-cpufreq.c:55:22: error: variable 'old_freq' set but not used From: kernel test robot To: "Rob Herring (Arm)" Cc: oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Viresh Kumar Date: Tue, 17 Sep 2024 11:52:24 +0800 . Subject: [PATCH] Bluetooth: btusb: Add MT7925 support for ID 0x13d3:0x3608 From: WangYuli To: marcel@holtmann.org, johan.hedberg@gmail.com, luiz.dentz@gmail.com, matthias.bgg@gmail.com, hello@felixjara.me, wangyuli@uniontech.com Cc: linux-bluetooth@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, aaron.ma@canonical.com, guanwentao@uniontech.com, zhanjun@uniontech.com Date: Tue, 17 Sep 2024 11:55:45 +0800 . Subject: [PATCH] arm: expressatt: fix pm8921_l6 regulator From: Rudraksha Gupta via B4 Relay To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rudraksha Gupta Date: Mon, 16 Sep 2024 21:48:35 -0700 . Subject: [syzbot] [erofs?] [mm?] BUG: unable to handle kernel NULL pointer dereference in filemap_read_folio (3) From: syzbot To: chao@kernel.org, dhavale@google.com, huyue2@coolpad.com, jefflexu@linux.alibaba.com, linux-erofs@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, syzkaller-bugs@googlegroups.com, xiang@kernel.org Date: Mon, 16 Sep 2024 21:59:31 -0700 . Subject: linux-next: duplicate patch in the rust tree From: Stephen Rothwell To: Miguel Ojeda , Andrew Morton Cc: Linux Kernel Mailing List , Linux Next Mailing List Date: Tue, 17 Sep 2024 14:59:41 +1000 . Subject: [PATCH 00/18] Staging: rtl8192e: 18 more Style guide variable renames From: Tree Davies To: gregkh@linuxfoundation.org, philipp.g.hortmann@gmail.com, anjan@momi.ca Cc: linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, Tree Davies Date: Mon, 16 Sep 2024 22:31:34 -0700 . Subject: [PATCH v3] x86/hyper-v: Fix hv tsc page based sched_clock for hibernation From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Daniel Lezcano , Michael Kelley Cc: linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org, namjain@linux.microsoft.com, stable@vger.kernel.org Date: Tue, 17 Sep 2024 11:09:17 +0530 . Subject: [syzbot] [usb?] INFO: task hung in adu_disconnect From: syzbot To: gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, syzkaller-bugs@googlegroups.com Date: Mon, 16 Sep 2024 22:45:32 -0700 . Subject: linux-next: Tree for Sep 17 From: Stephen Rothwell To: Linux Next Mailing List Cc: Linux Kernel Mailing List Date: Tue, 17 Sep 2024 15:56:50 +1000 . Subject: [GIT PULL] ksmbd server fixes From: Steve French To: Linus Torvalds Cc: LKML , CIFS , Namjae Jeon Date: Tue, 17 Sep 2024 01:23:30 -0500 Please pull the following changes since commit da3ea35007d0af457a0afc87e84fddaebc4e0b63: Linux 6.11-rc7 (2024-09-08 14:50:28 -0700) are available in the Git repository at: git://git.samba.org/ksmbd.git tags/6.12-rc-ksmbd-server-fixes-part1 for you to fetch changes up to c5a709f08d40b1a082e44ffcde1aea4d2822ddd5: ksmbd: handle caseless file creation (2024-09-14 00:03:15 -0500) ---------------------------------------------------------------- Four ksmbd server fixes, three for stable - Fix the issue where the directory can't be deleted if the share is on a file system that does not provide dot and dotdot entries. - Fix file creation failure if the parent name of pathname is case sensitive. - Fix write failure with FILE_APPEND_DATA flags. - Add reference count to connection struct to protect UAF of oplocks on multichannel. ---------------------------------------------------------------- Hobin Woo (1): ksmbd: make __dir_empty() compatible with POSIX Namjae Jeon (3): ksmbd: allow write with FILE_APPEND_DATA ksmbd: add refcnt to ksmbd_conn struct ksmbd: handle caseless file creation fs/smb/server/connection.c | 4 +++- fs/smb/server/connection.h | 1 + fs/smb/server/oplock.c | 55 ++++++++++++++++--------------------------------------- fs/smb/server/vfs.c | 19 ++++++++----------- fs/smb/server/vfs_cache.c | 3 +++ 5 files changed, 31 insertions(+), 51 deletions(-) -- Thanks, Steve . Subject: [PATCH] staging: comedi: ni_tio: Adjust clock period calculation in ni_tio_set_clock_src() From: Aleksandr Mishin To: H Hartley Sweeten Date: Tue, 17 Sep 2024 09:23:17 +0300 . Subject: [GIT PULL] pmdomain/cpuidle-psci updates for v6.12 From: Ulf Hansson To: Linus , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Viresh Kumar , Ulf Hansson , linux-arm-kernel@lists.infradead.org Date: Tue, 17 Sep 2024 08:46:53 +0200 Hi Linus, Here's the PR with pmdomain and cpuidle-psci updates for v6.12. Details about the highlights are as usual found in the signed tag. Please pull this in! Kind regards Ulf Hansson The following changes since commit 9ec87c5957ea9bf68d36f5e098605b585b2571e4: OPP: Fix support for required OPPs for multiple PM domains (2024-08-23 11:57:44 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git tags/pmdomain-v6.12 for you to fetch changes up to c6ccb691d484544636bc4a097574c5c135ccccda: pmdomain: core: Reduce debug summary table width (2024-09-13 13:41:33 +0200) ---------------------------------------------------------------- pmdomain core: - Add support for s2idle for CPU PM domains on PREEMPT_RT - Add device managed version of dev_pm_domain_attach|detach_list() - Improve layout of the debugfs summary table pmdomain providers: - amlogic: Remove obsolete vpu domain driver - bcm: raspberrypi: Add support for devices used as wakeup-sources - imx: Fixup clock handling for imx93 at driver remove - rockchip: Add gating support for RK3576 - rockchip: Add support for RK3576 SoC - Some OF parsing simplifications - Some simplifications by using dev_err_probe() and guard() pmdomain consumers: - qcom/media/venus: Convert to the device managed APIs for PM domains cpuidle-psci: - Add support for s2idle/s2ram for the hierarchical topology on PREEMPT_RT - Some OF parsing simplifications ---------------------------------------------------------------- Dario Binacchi (3): pmdomain: imx93-pd: replace dev_err() with dev_err_probe() pmdomain: imx93-pd: don't unprepare clocks on driver remove pmdomain: imx93-pd: drop the context variable "init_off" Detlev Casanova (2): pmdomain: rockchip: Add gating support pmdomain: rockchip: Add gating masks for rk3576 Dikshita Agarwal (2): PM: domains: add device managed version of dev_pm_domain_attach|detach_list() media: venus: use device managed APIs for power domains Finley Xiao (2): dt-bindings: power: Add support for RK3576 SoC pmdomain: rockchip: Add support for RK3576 SoC Geert Uytterhoeven (4): pmdomain: core: Harden inter-column space in debug summary pmdomain: core: Fix "managed by" alignment in debug summary pmdomain: core: Move mode_status_str() pmdomain: core: Reduce debug summary table width Hongbo Li (1): pmdomain: mediatek: make use of dev_err_cast_probe() Jerome Brunet (1): pmdomain: amlogic: remove obsolete vpu domain driver Jinjie Ruan (1): pmdomain: apple: Make apple_pmgr_reset_ops static Krzysztof Kozlowski (11): cpuidle: psci: Simplify with scoped for each OF child loop cpuidle: dt_idle_genpd: Simplify with scoped for each OF child loop pmdomain: rockchip: Simplify with scoped for each OF child loop pmdomain: rockchip: Simplify locking with guard() pmdomain: imx: gpc: Simplify with scoped for each OF child loop pmdomain: imx: gpcv2: Simplify with scoped for each OF child loop pmdomain: qcom: cpr: Simplify with dev_err_probe() pmdomain: qcom: cpr: Simplify locking with guard() pmdomain: qcom: rpmhpd: Simplify locking with guard() pmdomain: qcom: rpmpd: Simplify locking with guard() pmdomain: rockchip: Simplify dropping OF node reference Stefan Wahren (3): pmdomain: raspberrypi-power: Adjust packet definition pmdomain: raspberrypi-power: Add logging to rpi_firmware_set_power pmdomain: raspberrypi-power: set flag GENPD_FLAG_ACTIVE_WAKEUP Ulf Hansson (11): pmdomain: core: Enable s2idle for CPU PM domains on PREEMPT_RT pmdomain: core: Don't hold the genpd-lock when calling dev_pm_domain_set() pmdomain: core: Use dev_name() instead of kobject_get_path() in debugfs cpuidle: psci-domain: Enable system-wide suspend on PREEMPT_RT cpuidle: psci: Drop redundant assignment of CPUIDLE_FLAG_RCU_IDLE cpuidle: psci: Enable the hierarchical topology for s2ram on PREEMPT_RT cpuidle: psci: Enable the hierarchical topology for s2idle on PREEMPT_RT pmdomain: Merge branch fixes into next pmdomain: Merge branch fixes into next pmdomain: Merge branch dt into next pmdomain: Merge branch fixes into next Zhang Zekun (2): pmdomain: qcom-cpr: Use helper function for_each_available_child_of_node() pmdomain: qcom-cpr: Use scope based of_node_put() to simplify code. .../bindings/power/rockchip,power-controller.yaml | 1 + drivers/base/power/common.c | 45 +++ drivers/cpuidle/cpuidle-psci-domain.c | 17 +- drivers/cpuidle/cpuidle-psci.c | 26 +- drivers/cpuidle/dt_idle_genpd.c | 14 +- drivers/media/platform/qcom/venus/pm_helpers.c | 5 +- drivers/pmdomain/amlogic/Kconfig | 11 - drivers/pmdomain/amlogic/Makefile | 1 - drivers/pmdomain/amlogic/meson-gx-pwrc-vpu.c | 380 --------------------- drivers/pmdomain/apple/pmgr-pwrstate.c | 2 +- drivers/pmdomain/bcm/raspberrypi-power.c | 43 ++- drivers/pmdomain/core.c | 94 +++-- drivers/pmdomain/imx/gpc.c | 14 +- drivers/pmdomain/imx/gpcv2.c | 8 +- drivers/pmdomain/imx/imx93-pd.c | 22 +- drivers/pmdomain/mediatek/mtk-pm-domains.c | 6 +- drivers/pmdomain/qcom/cpr.c | 92 ++--- drivers/pmdomain/qcom/rpmhpd.c | 11 +- drivers/pmdomain/qcom/rpmpd.c | 20 +- drivers/pmdomain/rockchip/pm-domains.c | 118 +++++-- include/dt-bindings/power/rockchip,rk3576-power.h | 30 ++ include/linux/pm_domain.h | 16 +- 22 files changed, 373 insertions(+), 603 deletions(-) delete mode 100644 drivers/pmdomain/amlogic/meson-gx-pwrc-vpu.c create mode 100644 include/dt-bindings/power/rockchip,rk3576-power.h . Subject: [PATCH v2] driver core: bus: Remove an impossible error handling path in bus_add_driver() From: Zijun Hu To: Greg Kroah-Hartman , "Rafael J. Wysocki" Cc: Zijun Hu , linux-kernel@vger.kernel.org, Zijun Hu Date: Tue, 17 Sep 2024 14:49:34 +0800 . Subject: [PATCH v2] arm64: dts: imx8: Fix lvds0 device tree From: Diogo Silva To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, Frank.Li@nxp.com Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, diogompaissilva@gmail.com Date: Tue, 17 Sep 2024 08:58:01 +0200 . Subject: [PATCH] nullb: Adjust device size calculation in null_alloc_dev() From: Aleksandr Mishin To: Shaohua Li Date: Tue, 17 Sep 2024 10:07:29 +0300 . Subject: [PATCH] netfs, cifs: Fix mtime/ctime update for mmapped writes From: David Howells To: Steve French , Christian Brauner Date: Tue, 17 Sep 2024 08:54:28 +0100 . Subject: [PATCH] drm/panel: elida-kd35t133: transition to mipi_dsi wrapped functions From: Tejas Vipin To: neil.armstrong@linaro.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Cc: quic_jesszhan@quicinc.com, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Tejas Vipin Date: Tue, 17 Sep 2024 12:47:10 +0530 . Subject: [PATCH v2 0/2] ARM: dts: microchip: rng node name and label tweaks From: Alexander Dahl To: Conor Dooley Cc: Nicolas Ferre , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 09:27:08 +0200 . Subject: [PATCH] list: Remove duplicated and unused macro list_for_each_reverse From: Zijun Hu To: Greg Kroah-Hartman , Ingo Molnar Cc: Zijun Hu , linux-kernel@vger.kernel.org, Zijun Hu , stable@vger.kernel.org Date: Tue, 17 Sep 2024 15:28:18 +0800 . Subject: [PATCH] fbcon: Fix a NULL pointer dereference issue in fbcon_putcs From: Qianqiang Liu To: Helge Deller Cc: linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, stable@vger.kernel.org, syzbot+3d613ae53c031502687a@syzkaller.appspotmail.com Date: Tue, 17 Sep 2024 15:28:37 +0800 . Subject: [PATCH V2 0/7] mm: Use pxdp_get() for accessing page table entries From: Anshuman Khandual To: linux-mm@kvack.org Cc: Anshuman Khandual , Andrew Morton , David Hildenbrand , Ryan Roberts , "Mike Rapoport (IBM)" , Arnd Bergmann , x86@kernel.org, linux-m68k@lists.linux-m68k.org, linux-fsdevel@vger.kernel.org, kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Date: Tue, 17 Sep 2024 13:01:10 +0530 . Subject: ld.lld: error: relocation R_PPC_ADDR16_HI cannot be used against symbol 'init_task'; recompile with -fPIC From: kernel test robot To: Michael Haener Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Jarkko Sakkinen , Alexander Sverdlin , Krzysztof Kozlowski Date: Tue, 17 Sep 2024 15:50:18 +0800 . Subject: [PATCH] clk: si5341: Prevent division by zero in si5341_output_clk_determine_rate() From: Aleksandr Mishin To: Maxime Ripard Date: Tue, 17 Sep 2024 10:52:50 +0300 . Subject: [GIT PULL] smb3 client fixes From: Steve French To: Linus Torvalds Cc: LKML , CIFS Date: Tue, 17 Sep 2024 03:22:17 -0500 Please pull the following changes since commit 98f7e32f20d28ec452afb208f9cffc08448a2652: Linux 6.11 (2024-09-15 16:57:56 +0200) are available in the Git repository at: git://git.samba.org/sfrench/cifs-2.6.git tags/v6.12-rc-smb3-client-fixes-= part1 for you to fetch changes up to 5ac1f99fdd09d80223e8f47dffaea41a6563aace: smb: client: fix compression heuristic functions (2024-09-16 20:10:39 -05= 00) ---------------------------------------------------------------- SMB3 client fixes 11 cleanup changesets (moving duplicated code, removing unused code etc.) 7 fixes relating to "sfu" mount options (for better handling special file types) 6 SMB3.1.1 compression fixes/improvements ---------------------------------------------------------------- ChenXiaoSong (7): smb/client: rename cifs_ntsd to smb_ntsd smb/client: rename cifs_sid to smb_sid smb/client: rename cifs_acl to smb_acl smb/client: rename cifs_ace to smb_ace smb: move some duplicate definitions to common/smbacl.h smb: move SMB2 Status code to common header file smb: add comment to STATUS_MCA_OCCURED Enzo Matsumiya (3): smb: client: insert compression check/call on write requests smb: client: compress: LZ77 code improvements cleanup smb: client: fix compression heuristic functions Gaosheng Cui (1): cifs: Remove obsoleted declaration for cifs_dir_open Hongbo Li (1): smb: use LIST_HEAD() to simplify code Pali Roh=C3=A1r (7): cifs: Fix recognizing SFU symlinks cifs: Add support for reading SFU symlink location cifs: Put explicit zero byte into SFU block/char types cifs: Show debug message when SFU Fifo type was detected cifs: Recognize SFU socket type cifs: Add support for creating SFU symlinks cifs: Update SFU comments about fifos and sockets Qianqiang Liu (2): smb: client: compress: fix a potential issue of freeing an invalid po= inter smb: client: compress: fix an "illegal accesses" issue Shen Lichuan (1): smb: client: Use min() macro Steve French (1): smb3: mark compression as CONFIG_EXPERIMENTAL and fix missing compression operation Yuesong Li (1): cifs: convert to use ERR_CAST() fs/smb/client/Kconfig | 14 + fs/smb/client/Makefile | 2 + fs/smb/client/cifs_debug.c | 7 +- fs/smb/client/cifsacl.c | 226 +++--- fs/smb/client/cifsacl.h | 99 +-- fs/smb/client/cifsfs.h | 1 - fs/smb/client/cifsglob.h | 25 +- fs/smb/client/cifspdu.h | 6 - fs/smb/client/cifsproto.h | 28 +- fs/smb/client/cifssmb.c | 14 +- fs/smb/client/compress.c | 390 ++++++++++ fs/smb/client/compress.h | 90 +++ fs/smb/client/compress/lz77.c | 235 ++++++ fs/smb/client/compress/lz77.h | 15 + fs/smb/client/connect.c | 5 +- fs/smb/client/file.c | 7 +- fs/smb/client/fs_context.c | 20 +- fs/smb/client/inode.c | 42 +- fs/smb/client/link.c | 3 + fs/smb/client/misc.c | 9 +- fs/smb/client/smb1ops.c | 2 +- fs/smb/client/smb2file.c | 6 +- fs/smb/client/smb2inode.c | 6 +- fs/smb/client/smb2maperror.c | 2 +- fs/smb/client/smb2misc.c | 2 +- fs/smb/client/smb2ops.c | 98 ++- fs/smb/client/smb2pdu.c | 19 +- fs/smb/client/smb2pdu.h | 8 +- fs/smb/client/smb2proto.h | 2 +- fs/smb/client/smb2transport.c | 2 +- fs/smb/client/smbdirect.c | 6 +- fs/smb/client/transport.c | 4 + fs/smb/client/xattr.c | 4 +- fs/smb/{client =3D> common}/smb2status.h | 6 + fs/smb/common/smbacl.h | 121 ++++ fs/smb/server/oplock.c | 2 +- fs/smb/server/server.c | 2 +- fs/smb/server/smb2misc.c | 2 +- fs/smb/server/smb2pdu.c | 2 +- fs/smb/server/smb_common.c | 2 +- fs/smb/server/smbacl.h | 111 +-- fs/smb/server/smbstatus.h | 1822 ----------------------------------------------- fs/smb/server/transport_rdma.c | 2 +- 43 files changed, 1206 insertions(+), 2265 deletions(-) create mode 100644 fs/smb/client/compress.c create mode 100644 fs/smb/client/compress.h create mode 100644 fs/smb/client/compress/lz77.c create mode 100644 fs/smb/client/compress/lz77.h rename fs/smb/{client =3D> common}/smb2status.h (99%) create mode 100644 fs/smb/common/smbacl.h delete mode 100644 fs/smb/server/smbstatus.h -- Thanks, Steve . Subject: [PATCH v4 0/8] Add support for GE SUNH hot-pluggable connector From: Luca Ceresoli To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , Wolfram Sang , "Rafael J. Wysocki" , Lee Jones , Daniel Thompson , Jingoo Han , Helge Deller Cc: Paul Kocialkowski , =?utf-8?q?Herv=C3=A9_Codina?= , Thomas Petazzoni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-i2c@vger.kernel.org, linux-fbdev@vger.kernel.org, Paul Kocialkowski , Luca Ceresoli Date: Tue, 17 Sep 2024 10:53:04 +0200 . Subject: [syzbot] [f2fs?] kernel BUG in f2fs_invalidate_blocks From: syzbot To: chao@kernel.org, jaegeuk@kernel.org, linux-f2fs-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, syzkaller-bugs@googlegroups.com Date: Tue, 17 Sep 2024 01:41:25 -0700 . Subject: [PATCHv4 00/14] uprobe, bpf: Add session support From: Jiri Olsa To: Oleg Nesterov , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko Cc: bpf@vger.kernel.org, Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Steven Rostedt , Masami Hiramatsu , linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 10:50:10 +0200 . Subject: [GIT pull] x86/fpu for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:10 +0200 (CEST) Linus, please pull the latest x86/fpu branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-fpu-2024-09-= 17 up to: ba386777a30b: x86/elf: Add a new FPU buffer layout info to x86 core f= iles Provide FPU buffer layout in core dumps: Debuggers have guess the FPU buffer layout in core dumps, which is error prone. This is because AMD and Intel layouts differ. To avoid buggy heuristics add a ELF section which describes the buffer layout which can be retrieved by tools. Thanks, tglx ------------------> Vignesh Balasubramanian (1): x86/elf: Add a new FPU buffer layout info to x86 core files arch/x86/Kconfig | 1 + arch/x86/include/uapi/asm/elf.h | 16 ++++++++ arch/x86/kernel/fpu/xstate.c | 89 +++++++++++++++++++++++++++++++++++++++= ++ fs/binfmt_elf.c | 4 +- include/uapi/linux/elf.h | 1 + 5 files changed, 109 insertions(+), 2 deletions(-) create mode 100644 arch/x86/include/uapi/asm/elf.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 007bab9f2a0e..c15b4b3fb328 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -107,6 +107,7 @@ config X86 select ARCH_HAS_DEBUG_WX select ARCH_HAS_ZONE_DMA_SET if EXPERT select ARCH_HAVE_NMI_SAFE_CMPXCHG + select ARCH_HAVE_EXTRA_ELF_NOTES select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI select ARCH_MIGHT_HAVE_PC_PARPORT diff --git a/arch/x86/include/uapi/asm/elf.h b/arch/x86/include/uapi/asm/elf.h new file mode 100644 index 000000000000..468e135fa285 --- /dev/null +++ b/arch/x86/include/uapi/asm/elf.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_ASM_X86_ELF_H +#define _UAPI_ASM_X86_ELF_H + +#include + +struct x86_xfeat_component { + __u32 type; + __u32 size; + __u32 offset; + __u32 flags; +} __packed; + +_Static_assert(sizeof(struct x86_xfeat_component) % 4 =3D=3D 0, "x86_xfeat_c= omponent is not aligned"); + +#endif /* _UAPI_ASM_X86_ELF_H */ diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index c5a026fee5e0..f3a2e59a28e7 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include #include @@ -23,6 +24,8 @@ #include #include =20 +#include + #include "context.h" #include "internal.h" #include "legacy.h" @@ -1838,3 +1841,89 @@ int proc_pid_arch_status(struct seq_file *m, struct pi= d_namespace *ns, return 0; } #endif /* CONFIG_PROC_PID_ARCH_STATUS */ + +#ifdef CONFIG_COREDUMP +static const char owner_name[] =3D "LINUX"; + +/* + * Dump type, size, offset and flag values for every xfeature that is presen= t. + */ +static int dump_xsave_layout_desc(struct coredump_params *cprm) +{ + int num_records =3D 0; + int i; + + for_each_extended_xfeature(i, fpu_user_cfg.max_features) { + struct x86_xfeat_component xc =3D { + .type =3D i, + .size =3D xstate_sizes[i], + .offset =3D xstate_offsets[i], + /* reserved for future use */ + .flags =3D 0, + }; + + if (!dump_emit(cprm, &xc, sizeof(xc))) + return 0; + + num_records++; + } + return num_records; +} + +static u32 get_xsave_desc_size(void) +{ + u32 cnt =3D 0; + u32 i; + + for_each_extended_xfeature(i, fpu_user_cfg.max_features) + cnt++; + + return cnt * (sizeof(struct x86_xfeat_component)); +} + +int elf_coredump_extra_notes_write(struct coredump_params *cprm) +{ + int num_records =3D 0; + struct elf_note en; + + if (!fpu_user_cfg.max_features) + return 0; + + en.n_namesz =3D sizeof(owner_name); + en.n_descsz =3D get_xsave_desc_size(); + en.n_type =3D NT_X86_XSAVE_LAYOUT; + + if (!dump_emit(cprm, &en, sizeof(en))) + return 1; + if (!dump_emit(cprm, owner_name, en.n_namesz)) + return 1; + if (!dump_align(cprm, 4)) + return 1; + + num_records =3D dump_xsave_layout_desc(cprm); + if (!num_records) + return 1; + + /* Total size should be equal to the number of records */ + if ((sizeof(struct x86_xfeat_component) * num_records) !=3D en.n_descsz) + return 1; + + return 0; +} + +int elf_coredump_extra_notes_size(void) +{ + int size; + + if (!fpu_user_cfg.max_features) + return 0; + + /* .note header */ + size =3D sizeof(struct elf_note); + /* Name plus alignment to 4 bytes */ + size +=3D roundup(sizeof(owner_name), 4); + size +=3D get_xsave_desc_size(); + + return size; +} +#endif /* CONFIG_COREDUMP */ diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c index 19fa49cd9907..01bcbe7fdebd 100644 --- a/fs/binfmt_elf.c +++ b/fs/binfmt_elf.c @@ -2039,7 +2039,7 @@ static int elf_core_dump(struct coredump_params *cprm) { size_t sz =3D info.size; =20 - /* For cell spufs */ + /* For cell spufs and x86 xstate */ sz +=3D elf_coredump_extra_notes_size(); =20 phdr4note =3D kmalloc(sizeof(*phdr4note), GFP_KERNEL); @@ -2103,7 +2103,7 @@ static int elf_core_dump(struct coredump_params *cprm) if (!write_note_info(&info, cprm)) goto end_coredump; =20 - /* For cell spufs */ + /* For cell spufs and x86 xstate */ if (elf_coredump_extra_notes_write(cprm)) goto end_coredump; =20 diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b54b313bcf07..e30a9b47dc87 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -411,6 +411,7 @@ typedef struct elf64_shdr { #define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ /* Old binutils treats 0x203 as a CET state */ #define NT_X86_SHSTK 0x204 /* x86 SHSTK state */ +#define NT_X86_XSAVE_LAYOUT 0x205 /* XSAVE layout description */ #define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */ #define NT_S390_TIMER 0x301 /* s390 timer register */ #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */ . Subject: [GIT pull] x86/build for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:05 +0200 (CEST) Linus, please pull the latest x86/build branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-build-2024-0= 9-17 up to: ae94b263f5f6: x86: Ignore stack unwinding in KCOV Updates for KCOV instrumentation on x86: - Prevent spurious KCOV coverage in common_interrupt() - Fixup the KCOV Makefile directive which got stale due to a source file rename - Exclude stack unwinding from KCOV as it creates large amounts of uninteresting coverage - Provide a self test to validate that KCOV coverage of the interrupt handling code starts not before preempt count got updated. Thanks, tglx ------------------> Dmitry Vyukov (4): x86/entry: Remove unwanted instrumentation in common_interrupt() kcov: Add interrupt handling self test module: Fix KCOV-ignored file name x86: Ignore stack unwinding in KCOV arch/x86/include/asm/hardirq.h | 8 ++++++-- arch/x86/include/asm/idtentry.h | 6 +++--- arch/x86/kernel/Makefile | 8 ++++++++ kernel/kcov.c | 31 +++++++++++++++++++++++++++++++ kernel/module/Makefile | 2 +- lib/Kconfig.debug | 8 ++++++++ 6 files changed, 57 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h index c67fa6ad098a..6ffa8b75f4cd 100644 --- a/arch/x86/include/asm/hardirq.h +++ b/arch/x86/include/asm/hardirq.h @@ -69,7 +69,11 @@ extern u64 arch_irq_stat(void); #define local_softirq_pending_ref pcpu_hot.softirq_pending =20 #if IS_ENABLED(CONFIG_KVM_INTEL) -static inline void kvm_set_cpu_l1tf_flush_l1d(void) +/* + * This function is called from noinstr interrupt contexts + * and must be inlined to not get instrumentation. + */ +static __always_inline void kvm_set_cpu_l1tf_flush_l1d(void) { __this_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1); } @@ -84,7 +88,7 @@ static __always_inline bool kvm_get_cpu_l1tf_flush_l1d(void) return __this_cpu_read(irq_stat.kvm_cpu_l1tf_flush_l1d); } #else /* !IS_ENABLED(CONFIG_KVM_INTEL) */ -static inline void kvm_set_cpu_l1tf_flush_l1d(void) { } +static __always_inline void kvm_set_cpu_l1tf_flush_l1d(void) { } #endif /* IS_ENABLED(CONFIG_KVM_INTEL) */ =20 #endif /* _ASM_X86_HARDIRQ_H */ diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index d4f24499b256..ad5c68f0509d 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -212,8 +212,8 @@ __visible noinstr void func(struct pt_regs *regs, \ irqentry_state_t state =3D irqentry_enter(regs); \ u32 vector =3D (u32)(u8)error_code; \ \ + kvm_set_cpu_l1tf_flush_l1d(); \ instrumentation_begin(); \ - kvm_set_cpu_l1tf_flush_l1d(); \ run_irq_on_irqstack_cond(__##func, regs, vector); \ instrumentation_end(); \ irqentry_exit(regs, state); \ @@ -250,7 +250,6 @@ static void __##func(struct pt_regs *regs); \ \ static __always_inline void instr_##func(struct pt_regs *regs) \ { \ - kvm_set_cpu_l1tf_flush_l1d(); \ run_sysvec_on_irqstack_cond(__##func, regs); \ } \ \ @@ -258,6 +257,7 @@ __visible noinstr void func(struct pt_regs *regs) \ { \ irqentry_state_t state =3D irqentry_enter(regs); \ \ + kvm_set_cpu_l1tf_flush_l1d(); \ instrumentation_begin(); \ instr_##func (regs); \ instrumentation_end(); \ @@ -288,7 +288,6 @@ static __always_inline void __##func(struct pt_regs *regs= ); \ static __always_inline void instr_##func(struct pt_regs *regs) \ { \ __irq_enter_raw(); \ - kvm_set_cpu_l1tf_flush_l1d(); \ __##func (regs); \ __irq_exit_raw(); \ } \ @@ -297,6 +296,7 @@ __visible noinstr void func(struct pt_regs *regs) \ { \ irqentry_state_t state =3D irqentry_enter(regs); \ \ + kvm_set_cpu_l1tf_flush_l1d(); \ instrumentation_begin(); \ instr_##func (regs); \ instrumentation_end(); \ diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index a847180836e4..f7918980667a 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -35,6 +35,14 @@ KMSAN_SANITIZE_nmi.o :=3D n # If instrumentation of the following files is enabled, boot hangs during # first second. KCOV_INSTRUMENT_head$(BITS).o :=3D n +# These are called from save_stack_trace() on debug paths, +# and produce large amounts of uninteresting coverage. +KCOV_INSTRUMENT_stacktrace.o :=3D n +KCOV_INSTRUMENT_dumpstack.o :=3D n +KCOV_INSTRUMENT_dumpstack_$(BITS).o :=3D n +KCOV_INSTRUMENT_unwind_orc.o :=3D n +KCOV_INSTRUMENT_unwind_frame.o :=3D n +KCOV_INSTRUMENT_unwind_guess.o :=3D n =20 CFLAGS_irq.o :=3D -I $(src)/../include/asm/trace =20 diff --git a/kernel/kcov.c b/kernel/kcov.c index f0a69d402066..d9d4a0c04185 100644 --- a/kernel/kcov.c +++ b/kernel/kcov.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -1058,6 +1059,32 @@ u64 kcov_common_handle(void) } EXPORT_SYMBOL(kcov_common_handle); =20 +#ifdef CONFIG_KCOV_SELFTEST +static void __init selftest(void) +{ + unsigned long start; + + pr_err("running self test\n"); + /* + * Test that interrupts don't produce spurious coverage. + * The coverage callback filters out interrupt code, but only + * after the handler updates preempt count. Some code periodically + * leaks out of that section and leads to spurious coverage. + * It's hard to call the actual interrupt handler directly, + * so we just loop here for a bit waiting for a timer interrupt. + * We set kcov_mode to enable tracing, but don't setup the area, + * so any attempt to trace will crash. Note: we must not call any + * potentially traced functions in this region. + */ + start =3D jiffies; + current->kcov_mode =3D KCOV_MODE_TRACE_PC; + while ((jiffies - start) * MSEC_PER_SEC / HZ < 300) + ; + current->kcov_mode =3D 0; + pr_err("done running self test\n"); +} +#endif + static int __init kcov_init(void) { int cpu; @@ -1077,6 +1104,10 @@ static int __init kcov_init(void) */ debugfs_create_file_unsafe("kcov", 0600, NULL, NULL, &kcov_fops); =20 +#ifdef CONFIG_KCOV_SELFTEST + selftest(); +#endif + return 0; } =20 diff --git a/kernel/module/Makefile b/kernel/module/Makefile index a10b2b9a6fdf..50ffcc413b54 100644 --- a/kernel/module/Makefile +++ b/kernel/module/Makefile @@ -5,7 +5,7 @@ =20 # These are called from save_stack_trace() on slub debug path, # and produce insane amounts of uninteresting coverage. -KCOV_INSTRUMENT_module.o :=3D n +KCOV_INSTRUMENT_main.o :=3D n =20 obj-y +=3D main.o obj-y +=3D strict_rwx.o diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index a30c03a66172..270e367b3e6f 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -2173,6 +2173,14 @@ config KCOV_IRQ_AREA_SIZE soft interrupts. This specifies the size of those areas in the number of unsigned long words. =20 +config KCOV_SELFTEST + bool "Perform short selftests on boot" + depends on KCOV + help + Run short KCOV coverage collection selftests on boot. + On test failure, causes the kernel to panic. Recommended to be + enabled, ensuring critical functionality works as intended. + menuconfig RUNTIME_TESTING_MENU bool "Runtime Testing" default y . Subject: [GIT pull] x86/core for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:09 +0200 (CEST) Linus, please pull the latest x86/core branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-core-2024-09= -17 up to: 7424fc6b86c8: x86/traps: Enable UBSAN traps on x86 Enable UBSAN traps for x86, which provides better reporting through metadata encodeded into UD1. Thanks, tglx ------------------> Gatlin Newhouse (1): x86/traps: Enable UBSAN traps on x86 arch/x86/include/asm/bug.h | 12 ++++++++++ arch/x86/kernel/traps.c | 59 ++++++++++++++++++++++++++++++++++++++++++--= -- include/linux/ubsan.h | 5 ++++ lib/Kconfig.ubsan | 4 ++-- 4 files changed, 73 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h index a3ec87d198ac..806649c7f23d 100644 --- a/arch/x86/include/asm/bug.h +++ b/arch/x86/include/asm/bug.h @@ -13,6 +13,18 @@ #define INSN_UD2 0x0b0f #define LEN_UD2 2 =20 +/* + * In clang we have UD1s reporting UBSAN failures on X86, 64 and 32bit. + */ +#define INSN_ASOP 0x67 +#define OPCODE_ESCAPE 0x0f +#define SECOND_BYTE_OPCODE_UD1 0xb9 +#define SECOND_BYTE_OPCODE_UD2 0x0b + +#define BUG_NONE 0xffff +#define BUG_UD1 0xfffe +#define BUG_UD2 0xfffd + #ifdef CONFIG_GENERIC_BUG =20 #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 4fa0b17e5043..415881607c5d 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -42,6 +42,7 @@ #include #include #include +#include =20 #include #include @@ -91,6 +92,47 @@ __always_inline int is_valid_bugaddr(unsigned long addr) return *(unsigned short *)addr =3D=3D INSN_UD2; } =20 +/* + * Check for UD1 or UD2, accounting for Address Size Override Prefixes. + * If it's a UD1, get the ModRM byte to pass along to UBSan. + */ +__always_inline int decode_bug(unsigned long addr, u32 *imm) +{ + u8 v; + + if (addr < TASK_SIZE_MAX) + return BUG_NONE; + + v =3D *(u8 *)(addr++); + if (v =3D=3D INSN_ASOP) + v =3D *(u8 *)(addr++); + if (v !=3D OPCODE_ESCAPE) + return BUG_NONE; + + v =3D *(u8 *)(addr++); + if (v =3D=3D SECOND_BYTE_OPCODE_UD2) + return BUG_UD2; + + if (!IS_ENABLED(CONFIG_UBSAN_TRAP) || v !=3D SECOND_BYTE_OPCODE_UD1) + return BUG_NONE; + + /* Retrieve the immediate (type value) for the UBSAN UD1 */ + v =3D *(u8 *)(addr++); + if (X86_MODRM_RM(v) =3D=3D 4) + addr++; + + *imm =3D 0; + if (X86_MODRM_MOD(v) =3D=3D 1) + *imm =3D *(u8 *)addr; + else if (X86_MODRM_MOD(v) =3D=3D 2) + *imm =3D *(u32 *)addr; + else + WARN_ONCE(1, "Unexpected MODRM_MOD: %u\n", X86_MODRM_MOD(v)); + + return BUG_UD1; +} + + static nokprobe_inline int do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, struct pt_regs *regs, long error_code) @@ -216,6 +258,8 @@ static inline void handle_invalid_op(struct pt_regs *regs) static noinstr bool handle_bug(struct pt_regs *regs) { bool handled =3D false; + int ud_type; + u32 imm; =20 /* * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug() @@ -223,7 +267,8 @@ static noinstr bool handle_bug(struct pt_regs *regs) * irqentry_enter(). */ kmsan_unpoison_entry_regs(regs); - if (!is_valid_bugaddr(regs->ip)) + ud_type =3D decode_bug(regs->ip, &imm); + if (ud_type =3D=3D BUG_NONE) return handled; =20 /* @@ -236,10 +281,14 @@ static noinstr bool handle_bug(struct pt_regs *regs) */ if (regs->flags & X86_EFLAGS_IF) raw_local_irq_enable(); - if (report_bug(regs->ip, regs) =3D=3D BUG_TRAP_TYPE_WARN || - handle_cfi_failure(regs) =3D=3D BUG_TRAP_TYPE_WARN) { - regs->ip +=3D LEN_UD2; - handled =3D true; + if (ud_type =3D=3D BUG_UD2) { + if (report_bug(regs->ip, regs) =3D=3D BUG_TRAP_TYPE_WARN || + handle_cfi_failure(regs) =3D=3D BUG_TRAP_TYPE_WARN) { + regs->ip +=3D LEN_UD2; + handled =3D true; + } + } else if (IS_ENABLED(CONFIG_UBSAN_TRAP)) { + pr_crit("%s at %pS\n", report_ubsan_failure(regs, imm), (void *)regs->ip); } if (regs->flags & X86_EFLAGS_IF) raw_local_irq_disable(); diff --git a/include/linux/ubsan.h b/include/linux/ubsan.h index bff7445498de..d8219cbe09ff 100644 --- a/include/linux/ubsan.h +++ b/include/linux/ubsan.h @@ -4,6 +4,11 @@ =20 #ifdef CONFIG_UBSAN_TRAP const char *report_ubsan_failure(struct pt_regs *regs, u32 check_type); +#else +static inline const char *report_ubsan_failure(struct pt_regs *regs, u32 che= ck_type) +{ + return NULL; +} #endif =20 #endif diff --git a/lib/Kconfig.ubsan b/lib/Kconfig.ubsan index bdda600f8dfb..1d4aa7a83b3a 100644 --- a/lib/Kconfig.ubsan +++ b/lib/Kconfig.ubsan @@ -29,8 +29,8 @@ config UBSAN_TRAP =20 Also note that selecting Y will cause your kernel to Oops with an "illegal instruction" error with no further details - when a UBSAN violation occurs. (Except on arm64, which will - report which Sanitizer failed.) This may make it hard to + when a UBSAN violation occurs. (Except on arm64 and x86, which + will report which Sanitizer failed.) This may make it hard to determine whether an Oops was caused by UBSAN or to figure out the details of a UBSAN violation. It makes the kernel log output less useful for bug reports. . Subject: [GIT pull] x86/cleanups for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:07 +0200 (CEST) Linus, please pull the latest x86/cleanups branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-cleanups-202= 4-09-17 up to: a678164aadbf: x86/EISA: Dereference memory directly instead of using = readl() A set of cleanups across x86: - Use memremap() for the EISA probe instrad of ioremap(). EISA is strictly memory and not MMIO - Cleanups and enhancement all over the place Thanks, tglx ------------------> Gaosheng Cui (1): x86/mtrr: Remove obsolete declaration for mtrr_bp_restore() Kai Huang (3): x86/sgx: Fix a W=3D1 build warning in function comment x86/kexec: Fix a comment of swap_pages() assembly x86/kexec: Add comments around swap_pages() assembly to improve readabi= lity Maciej W. Rozycki (2): x86/EISA: Use memremap() to probe for the EISA BIOS signature x86/EISA: Dereference memory directly instead of using readl() Nathan Chancellor (1): x86/cpu_entry_area: Annotate percpu_setup_exception_stacks() as __init Uros Bizjak (1): x86/boot/64: Strip percpu address space when setting up GDT descriptors WangYuli (1): x86/cpu: Clarify the error message when BIOS does not support SGX Yue Haibing (1): x86/extable: Remove unused declaration fixup_bug() arch/x86/include/asm/extable.h | 1 - arch/x86/include/asm/mtrr.h | 2 -- arch/x86/kernel/cpu/feat_ctl.c | 2 +- arch/x86/kernel/cpu/sgx/main.c | 2 +- arch/x86/kernel/eisa.c | 8 ++++---- arch/x86/kernel/head64.c | 3 ++- arch/x86/kernel/relocate_kernel_64.S | 10 +++++++--- arch/x86/mm/cpu_entry_area.c | 2 +- 8 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/extable.h b/arch/x86/include/asm/extable.h index eeed395c3177..a0e0c6b50155 100644 --- a/arch/x86/include/asm/extable.h +++ b/arch/x86/include/asm/extable.h @@ -37,7 +37,6 @@ struct pt_regs; =20 extern int fixup_exception(struct pt_regs *regs, int trapnr, unsigned long error_code, unsigned long fault_addr); -extern int fixup_bug(struct pt_regs *regs, int trapnr); extern int ex_get_fixup_type(unsigned long ip); extern void early_fixup_exception(struct pt_regs *regs, int trapnr); =20 diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 090d658a85a6..4218248083d9 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -69,7 +69,6 @@ extern int mtrr_add_page(unsigned long base, unsigned long = size, unsigned int type, bool increment); extern int mtrr_del(int reg, unsigned long base, unsigned long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); -extern void mtrr_bp_restore(void); extern int mtrr_trim_uncached_memory(unsigned long end_pfn); extern int amd_special_default_mtrr(void); void mtrr_disable(void); @@ -117,7 +116,6 @@ static inline int mtrr_trim_uncached_memory(unsigned long= end_pfn) return 0; } #define mtrr_bp_init() do {} while (0) -#define mtrr_bp_restore() do {} while (0) #define mtrr_disable() do {} while (0) #define mtrr_enable() do {} while (0) #define mtrr_generic_set_state() do {} while (0) diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c index 1640ae76548f..4a4118784c13 100644 --- a/arch/x86/kernel/cpu/feat_ctl.c +++ b/arch/x86/kernel/cpu/feat_ctl.c @@ -188,7 +188,7 @@ void init_ia32_feat_ctl(struct cpuinfo_x86 *c) update_sgx: if (!(msr & FEAT_CTL_SGX_ENABLED)) { if (enable_sgx_kvm || enable_sgx_driver) - pr_err_once("SGX disabled by BIOS.\n"); + pr_err_once("SGX disabled or unsupported by BIOS.\n"); clear_cpu_cap(c, X86_FEATURE_SGX); return; } diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 27892e57c4ef..1a000acd933a 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -732,7 +732,7 @@ int arch_memory_failure(unsigned long pfn, int flags) return 0; } =20 -/** +/* * A section metric is concatenated in a way that @low bits 12-31 define the * bits 12-31 of the metric and @high bits 0-19 define the bits 32-51 of the * metric. diff --git a/arch/x86/kernel/eisa.c b/arch/x86/kernel/eisa.c index 53935b4d62e3..9535a6507db7 100644 --- a/arch/x86/kernel/eisa.c +++ b/arch/x86/kernel/eisa.c @@ -11,15 +11,15 @@ =20 static __init int eisa_bus_probe(void) { - void __iomem *p; + u32 *p; =20 if ((xen_pv_domain() && !xen_initial_domain()) || cc_platform_has(CC_ATTR_G= UEST_SEV_SNP)) return 0; =20 - p =3D ioremap(0x0FFFD9, 4); - if (p && readl(p) =3D=3D 'E' + ('I' << 8) + ('S' << 16) + ('A' << 24)) + p =3D memremap(0x0FFFD9, 4, MEMREMAP_WB); + if (p && *p =3D=3D 'E' + ('I' << 8) + ('S' << 16) + ('A' << 24)) EISA_bus =3D 1; - iounmap(p); + memunmap(p); return 0; } subsys_initcall(eisa_bus_probe); diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index a817ed0724d1..4b9d4557fc94 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -559,10 +559,11 @@ void early_setup_idt(void) */ void __head startup_64_setup_gdt_idt(void) { + struct desc_struct *gdt =3D (void *)(__force unsigned long)init_per_cpu_var= (gdt_page.gdt); void *handler =3D NULL; =20 struct desc_ptr startup_gdt_descr =3D { - .address =3D (unsigned long)&RIP_REL_REF(init_per_cpu_var(gdt_page.gdt)), + .address =3D (unsigned long)&RIP_REL_REF(*gdt), .size =3D GDT_SIZE - 1, }; =20 diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_= kernel_64.S index 042c9a0334e9..e9e88c342f75 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -170,6 +170,7 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_mapped) wbinvd .Lsme_off: =20 + /* Save the preserve_context to %r11 as swap_pages clobbers %rcx. */ movq %rcx, %r11 call swap_pages =20 @@ -258,7 +259,7 @@ SYM_CODE_END(virtual_mapped) /* Do the copies */ SYM_CODE_START_LOCAL_NOALIGN(swap_pages) UNWIND_HINT_END_OF_STACK - movq %rdi, %rcx /* Put the page_list in %rcx */ + movq %rdi, %rcx /* Put the indirection_page in %rcx */ xorl %edi, %edi xorl %esi, %esi jmp 1f @@ -289,18 +290,21 @@ SYM_CODE_START_LOCAL_NOALIGN(swap_pages) movq %rcx, %rsi /* For ever source page do a copy */ andq $0xfffffffffffff000, %rsi =20 - movq %rdi, %rdx - movq %rsi, %rax + movq %rdi, %rdx /* Save destination page to %rdx */ + movq %rsi, %rax /* Save source page to %rax */ =20 + /* copy source page to swap page */ movq %r10, %rdi movl $512, %ecx rep ; movsq =20 + /* copy destination page to source page */ movq %rax, %rdi movq %rdx, %rsi movl $512, %ecx rep ; movsq =20 + /* copy swap page to destination page */ movq %rdx, %rdi movq %r10, %rsi movl $512, %ecx diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c index e91500a80963..575f863f3c75 100644 --- a/arch/x86/mm/cpu_entry_area.c +++ b/arch/x86/mm/cpu_entry_area.c @@ -164,7 +164,7 @@ static void __init percpu_setup_exception_stacks(unsigned= int cpu) } } #else -static inline void percpu_setup_exception_stacks(unsigned int cpu) +static void __init percpu_setup_exception_stacks(unsigned int cpu) { struct cpu_entry_area *cea =3D get_cpu_entry_area(cpu); =20 . Subject: [GIT pull] x86/platform for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:17 +0200 (CEST) Linus, please pull the latest x86/platform branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-platform-202= 4-09-17 up to: 22f426972655: x86/platform/uv: Remove unused declaration uv_irq_2_mmr= _info() Remove a stale declaration from the UV platform code Thanks, tglx ------------------> Yue Haibing (1): x86/platform/uv: Remove unused declaration uv_irq_2_mmr_info() arch/x86/include/asm/uv/uv_irq.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/include/asm/uv/uv_irq.h b/arch/x86/include/asm/uv/uv_ir= q.h index d6b17c760622..1876b5edd142 100644 --- a/arch/x86/include/asm/uv/uv_irq.h +++ b/arch/x86/include/asm/uv/uv_irq.h @@ -31,7 +31,6 @@ enum { UV_AFFINITY_CPU }; =20 -extern int uv_irq_2_mmr_info(int, unsigned long *, int *); extern int uv_setup_irq(char *, int, int, unsigned long, int); extern void uv_teardown_irq(unsigned int); =20 . Subject: [GIT pull] x86/fred for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:12 +0200 (CEST) Linus, please pull the latest x86/fred branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-fred-2024-09= -17 up to: fe85ee391966: x86/entry: Set FRED RSP0 on return to userspace instead= of context switch Updates for x86 FRED: - Enable FRED right after init_mem_mapping() because at that point the early IDT fault handler is replaced by the real fault handler. The real fault handler retrieves the faulting address from the stack frame and not from CR2 when the FRED feature is set. But that obviously only works when FRED is enabled in the CPU as well. - Set SS to __KERNEL_DS when enabling FRED to prevent a corner case where ERETS can observe a SS mismatch and raises a #GP. Thanks, tglx ------------------> Andrew Cooper (1): x86/msr: Switch between WRMSRNS and WRMSR with the alternatives mechani= sm Xin Li (Intel) (6): x86/fred: Parse cmdline param "fred=3D" in cpu_parse_early_param() x86/fred: Move FRED RSP initialization into a separate function x86/fred: Enable FRED right after init_mem_mapping() x86/fred: Set SS to __KERNEL_DS when enabling FRED x86/entry: Test ti_work for zero before processing individual bits x86/entry: Set FRED RSP0 on return to userspace instead of context swit= ch arch/x86/include/asm/entry-common.h | 13 +++++++++-- arch/x86/include/asm/fred.h | 23 ++++++++++++++++++- arch/x86/include/asm/msr.h | 25 +++++++++------------ arch/x86/include/asm/processor.h | 3 ++- arch/x86/include/asm/switch_to.h | 6 +---- arch/x86/kernel/cpu/common.c | 22 ++++++++++++++++-- arch/x86/kernel/cpu/cpuid-deps.c | 1 - arch/x86/kernel/fred.c | 45 +++++++++++++++++++++++++++++------= -- arch/x86/kernel/setup.c | 7 +++++- arch/x86/kernel/smpboot.c | 2 +- arch/x86/kernel/traps.c | 28 +---------------------- 11 files changed, 111 insertions(+), 64 deletions(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/entry= -common.h index fb2809b20b0a..77d20555e04d 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 /* Check that the stack and regs on entry from user mode are sane. */ static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) @@ -44,8 +45,7 @@ static __always_inline void arch_enter_from_user_mode(struc= t pt_regs *regs) } #define arch_enter_from_user_mode arch_enter_from_user_mode =20 -static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, - unsigned long ti_work) +static inline void arch_exit_work(unsigned long ti_work) { if (ti_work & _TIF_USER_RETURN_NOTIFY) fire_user_return_notifiers(); @@ -56,6 +56,15 @@ static inline void arch_exit_to_user_mode_prepare(struct p= t_regs *regs, fpregs_assert_state_consistent(); if (unlikely(ti_work & _TIF_NEED_FPU_LOAD)) switch_fpu_return(); +} + +static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, + unsigned long ti_work) +{ + if (IS_ENABLED(CONFIG_X86_DEBUG_FPU) || unlikely(ti_work)) + arch_exit_work(ti_work); + + fred_update_rsp0(); =20 #ifdef CONFIG_COMPAT /* diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index e86c7ba32435..25ca00bd70e8 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -36,6 +36,7 @@ =20 #ifdef CONFIG_X86_FRED #include +#include =20 #include =20 @@ -84,13 +85,33 @@ static __always_inline void fred_entry_from_kvm(unsigned = int type, unsigned int } =20 void cpu_init_fred_exceptions(void); +void cpu_init_fred_rsps(void); void fred_complete_exception_setup(void); =20 +DECLARE_PER_CPU(unsigned long, fred_rsp0); + +static __always_inline void fred_sync_rsp0(unsigned long rsp0) +{ + __this_cpu_write(fred_rsp0, rsp0); +} + +static __always_inline void fred_update_rsp0(void) +{ + unsigned long rsp0 =3D (unsigned long) task_stack_page(current) + THREAD_SI= ZE; + + if (cpu_feature_enabled(X86_FEATURE_FRED) && (__this_cpu_read(fred_rsp0) != =3D rsp0)) { + wrmsrns(MSR_IA32_FRED_RSP0, rsp0); + __this_cpu_write(fred_rsp0, rsp0); + } +} #else /* CONFIG_X86_FRED */ static __always_inline unsigned long fred_event_data(struct pt_regs *regs) {= return 0; } static inline void cpu_init_fred_exceptions(void) { } +static inline void cpu_init_fred_rsps(void) { } static inline void fred_complete_exception_setup(void) { } -static __always_inline void fred_entry_from_kvm(unsigned int type, unsigned = int vector) { } +static inline void fred_entry_from_kvm(unsigned int type, unsigned int vecto= r) { } +static inline void fred_sync_rsp0(unsigned long rsp0) { } +static inline void fred_update_rsp0(void) { } #endif /* CONFIG_X86_FRED */ #endif /* !__ASSEMBLY__ */ =20 diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index d642037f9ed5..001853541f1e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -99,19 +99,6 @@ static __always_inline void __wrmsr(unsigned int msr, u32 = low, u32 high) : : "c" (msr), "a"(low), "d" (high) : "memory"); } =20 -/* - * WRMSRNS behaves exactly like WRMSR with the only difference being - * that it is not a serializing instruction by default. - */ -static __always_inline void __wrmsrns(u32 msr, u32 low, u32 high) -{ - /* Instruction opcode for WRMSRNS; supported in binutils >=3D 2.40. */ - asm volatile("1: .byte 0x0f,0x01,0xc6\n" - "2:\n" - _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) - : : "c" (msr), "a"(low), "d" (high)); -} - #define native_rdmsr(msr, val1, val2) \ do { \ u64 __val =3D __rdmsr((msr)); \ @@ -312,9 +299,19 @@ do { \ =20 #endif /* !CONFIG_PARAVIRT_XXL */ =20 +/* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ +#define WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) + +/* Non-serializing WRMSR, when available. Falls back to a serializing WRMSR= . */ static __always_inline void wrmsrns(u32 msr, u64 val) { - __wrmsrns(msr, val, val >> 32); + /* + * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redundant + * DS prefix to avoid a trailing NOP. + */ + asm volatile("1: " ALTERNATIVE("ds wrmsr", WRMSRNS, X86_FEATURE_WRMSRNS) + "2: " _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) + : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))); } =20 /* diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processo= r.h index a75a07f4931f..399f7d1c4c61 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -582,7 +582,8 @@ extern void switch_gdt_and_percpu_base(int); extern void load_direct_gdt(int); extern void load_fixmap_gdt(int); extern void cpu_init(void); -extern void cpu_init_exception_handling(void); +extern void cpu_init_exception_handling(bool boot_cpu); +extern void cpu_init_replace_early_idt(void); extern void cr4_init(void); =20 extern void set_task_blockstep(struct task_struct *task, bool on); diff --git a/arch/x86/include/asm/switch_to.h b/arch/x86/include/asm/switch_t= o.h index c3bd0c0758c9..75248546403d 100644 --- a/arch/x86/include/asm/switch_to.h +++ b/arch/x86/include/asm/switch_to.h @@ -70,13 +70,9 @@ static inline void update_task_stack(struct task_struct *t= ask) #ifdef CONFIG_X86_32 this_cpu_write(cpu_tss_rw.x86_tss.sp1, task->thread.sp0); #else - if (cpu_feature_enabled(X86_FEATURE_FRED)) { - /* WRMSRNS is a baseline feature for FRED. */ - wrmsrns(MSR_IA32_FRED_RSP0, (unsigned long)task_stack_page(task) + THREAD_= SIZE); - } else if (cpu_feature_enabled(X86_FEATURE_XENPV)) { + if (!cpu_feature_enabled(X86_FEATURE_FRED) && cpu_feature_enabled(X86_FEATU= RE_XENPV)) /* Xen PV enters the kernel on the thread stack. */ load_sp0(task_top_of_stack(task)); - } #endif } =20 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index d4e539d4e158..a4735d9b5a1d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1510,6 +1510,11 @@ static void __init cpu_parse_early_param(void) if (cmdline_find_option_bool(boot_command_line, "nousershstk")) setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); =20 + /* Minimize the gap between FRED is available and available but disabled. */ + arglen =3D cmdline_find_option(boot_command_line, "fred", arg, sizeof(arg)); + if (arglen !=3D 2 || strncmp(arg, "on", 2)) + setup_clear_cpu_cap(X86_FEATURE_FRED); + arglen =3D cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof= (arg)); if (arglen <=3D 0) return; @@ -2171,7 +2176,7 @@ static inline void tss_setup_io_bitmap(struct tss_struc= t *tss) * Setup everything needed to handle exceptions from the IDT, including the = IST * exceptions which use paranoid_entry(). */ -void cpu_init_exception_handling(void) +void cpu_init_exception_handling(bool boot_cpu) { struct tss_struct *tss =3D this_cpu_ptr(&cpu_tss_rw); int cpu =3D raw_smp_processor_id(); @@ -2190,10 +2195,23 @@ void cpu_init_exception_handling(void) /* GHCB needs to be setup to handle #VC. */ setup_ghcb(); =20 + if (cpu_feature_enabled(X86_FEATURE_FRED)) { + /* The boot CPU has enabled FRED during early boot */ + if (!boot_cpu) + cpu_init_fred_exceptions(); + + cpu_init_fred_rsps(); + } else { + load_current_idt(); + } +} + +void __init cpu_init_replace_early_idt(void) +{ if (cpu_feature_enabled(X86_FEATURE_FRED)) cpu_init_fred_exceptions(); else - load_current_idt(); + idt_setup_early_pf(); } =20 /* diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-dep= s.c index b7d9f530ae16..8bd84114c2d9 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -83,7 +83,6 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, { X86_FEATURE_FRED, X86_FEATURE_LKGS }, - { X86_FEATURE_FRED, X86_FEATURE_WRMSRNS }, {} }; =20 diff --git a/arch/x86/kernel/fred.c b/arch/x86/kernel/fred.c index 4bcd8791ad96..8d32c3f48abc 100644 --- a/arch/x86/kernel/fred.c +++ b/arch/x86/kernel/fred.c @@ -21,17 +21,53 @@ =20 #define FRED_STKLVL(vector, lvl) ((lvl) << (2 * (vector))) =20 +DEFINE_PER_CPU(unsigned long, fred_rsp0); +EXPORT_PER_CPU_SYMBOL(fred_rsp0); + void cpu_init_fred_exceptions(void) { /* When FRED is enabled by default, remove this log message */ pr_info("Initialize FRED on CPU%d\n", smp_processor_id()); =20 + /* + * If a kernel event is delivered before a CPU goes to user level for + * the first time, its SS is NULL thus NULL is pushed into the SS field + * of the FRED stack frame. But before ERETS is executed, the CPU may + * context switch to another task and go to user level. Then when the + * CPU comes back to kernel mode, SS is changed to __KERNEL_DS. Later + * when ERETS is executed to return from the kernel event handler, a #GP + * fault is generated because SS doesn't match the SS saved in the FRED + * stack frame. + * + * Initialize SS to __KERNEL_DS when enabling FRED to avoid such #GPs. + */ + loadsegment(ss, __KERNEL_DS); + wrmsrl(MSR_IA32_FRED_CONFIG, /* Reserve for CALL emulation */ FRED_CONFIG_REDZONE | FRED_CONFIG_INT_STKLVL(0) | FRED_CONFIG_ENTRYPOINT(asm_fred_entrypoint_user)); =20 + wrmsrl(MSR_IA32_FRED_STKLVLS, 0); + wrmsrl(MSR_IA32_FRED_RSP0, 0); + wrmsrl(MSR_IA32_FRED_RSP1, 0); + wrmsrl(MSR_IA32_FRED_RSP2, 0); + wrmsrl(MSR_IA32_FRED_RSP3, 0); + + /* Enable FRED */ + cr4_set_bits(X86_CR4_FRED); + /* Any further IDT use is a bug */ + idt_invalidate(); + + /* Use int $0x80 for 32-bit system calls in FRED mode */ + setup_clear_cpu_cap(X86_FEATURE_SYSENTER32); + setup_clear_cpu_cap(X86_FEATURE_SYSCALL32); +} + +/* Must be called after setup_cpu_entry_areas() */ +void cpu_init_fred_rsps(void) +{ /* * The purpose of separate stacks for NMI, #DB and #MC *in the kernel* * (remember that user space faults are always taken on stack level 0) @@ -47,13 +83,4 @@ void cpu_init_fred_exceptions(void) wrmsrl(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); wrmsrl(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); wrmsrl(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); - - /* Enable FRED */ - cr4_set_bits(X86_CR4_FRED); - /* Any further IDT use is a bug */ - idt_invalidate(); - - /* Use int $0x80 for 32-bit system calls in FRED mode */ - setup_clear_cpu_cap(X86_FEATURE_SYSENTER32); - setup_clear_cpu_cap(X86_FEATURE_SYSCALL32); } diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 6129dc2ba784..f1fea506e20f 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1039,7 +1039,12 @@ void __init setup_arch(char **cmdline_p) =20 init_mem_mapping(); =20 - idt_setup_early_pf(); + /* + * init_mem_mapping() relies on the early IDT page fault handling. + * Now either enable FRED or install the real page fault handler + * for 64-bit in the IDT. + */ + cpu_init_replace_early_idt(); =20 /* * Update mmu_cr4_features (and, indirectly, trampoline_cr4_features) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 0c35207320cb..dc4fff8fccce 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -246,7 +246,7 @@ static void notrace start_secondary(void *unused) __flush_tlb_all(); } =20 - cpu_init_exception_handling(); + cpu_init_exception_handling(false); =20 /* * Load the microcode before reaching the AP alive synchronization diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 4fa0b17e5043..197d5888b0e2 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1402,34 +1402,8 @@ DEFINE_IDTENTRY_SW(iret_error) } #endif =20 -/* Do not enable FRED by default yet. */ -static bool enable_fred __ro_after_init =3D false; - -#ifdef CONFIG_X86_FRED -static int __init fred_setup(char *str) -{ - if (!str) - return -EINVAL; - - if (!cpu_feature_enabled(X86_FEATURE_FRED)) - return 0; - - if (!strcmp(str, "on")) - enable_fred =3D true; - else if (!strcmp(str, "off")) - enable_fred =3D false; - else - pr_warn("invalid FRED option: 'fred=3D%s'\n", str); - return 0; -} -early_param("fred", fred_setup); -#endif - void __init trap_init(void) { - if (cpu_feature_enabled(X86_FEATURE_FRED) && !enable_fred) - setup_clear_cpu_cap(X86_FEATURE_FRED); - /* Init cpu_entry_area before IST entries are set up */ setup_cpu_entry_areas(); =20 @@ -1437,7 +1411,7 @@ void __init trap_init(void) sev_es_init_vc_handling(); =20 /* Initialize TSS before setting up traps so ISTs work */ - cpu_init_exception_handling(); + cpu_init_exception_handling(true); =20 /* Setup traps as cpu_init() might #GP */ if (!cpu_feature_enabled(X86_FEATURE_FRED)) . Subject: [GIT pull] x86/timers for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:19 +0200 (CEST) Linus, please pull the latest x86/timers branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-timers-2024-= 09-17 up to: e7ff4ebffe3b: x86/tsc: Check for sockets instead of CPUs to make code= match comment Updates for x86 timers: - Use the topology information of number of packages for making the decision about TSC trust instead of using the number of online nodes which is not reflecting the real topology. - Stop the PIT timer 0 when its not in use as to stop pointless emulation in the VMM. - Fix the PIT timer stop sequence for timer 0 so it truly stops both real hardware and buggy VMM emulations. Thanks, tglx ------------------> David Woodhouse (2): x86/i8253: Disable PIT timer 0 when not in use clockevents/drivers/i8253: Fix stop sequence for timer 0 Feng Tang (1): x86/tsc: Use topology_max_packages() to get package number Paul E. McKenney (1): x86/tsc: Check for sockets instead of CPUs to make code match comment arch/x86/kernel/cpu/mshyperv.c | 11 ---------- arch/x86/kernel/i8253.c | 11 ++++++++-- arch/x86/kernel/tsc.c | 10 ++++----- drivers/clocksource/i8253.c | 49 +++++++++++++++++++++++++++++-----------= -- include/linux/i8253.h | 2 +- 5 files changed, 48 insertions(+), 35 deletions(-) diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index e0fd57a8ba84..3d4237f27569 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -522,16 +521,6 @@ static void __init ms_hyperv_init_platform(void) if (efi_enabled(EFI_BOOT)) x86_platform.get_nmi_reason =3D hv_get_nmi_reason; =20 - /* - * Hyper-V VMs have a PIT emulation quirk such that zeroing the - * counter register during PIT shutdown restarts the PIT. So it - * continues to interrupt @18.2 HZ. Setting i8253_clear_counter - * to false tells pit_shutdown() not to zero the counter so that - * the PIT really is shutdown. Generation 2 VMs don't have a PIT, - * and setting this value has no effect. - */ - i8253_clear_counter_on_shutdown =3D false; - #if IS_ENABLED(CONFIG_HYPERV) if ((hv_get_isolation_type() =3D=3D HV_ISOLATION_TYPE_VBS) || ms_hyperv.paravisor_present) diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c index 2b7999a1a50a..80e262bb627f 100644 --- a/arch/x86/kernel/i8253.c +++ b/arch/x86/kernel/i8253.c @@ -8,6 +8,7 @@ #include #include =20 +#include #include #include #include @@ -39,9 +40,15 @@ static bool __init use_pit(void) =20 bool __init pit_timer_init(void) { - if (!use_pit()) + if (!use_pit()) { + /* + * Don't just ignore the PIT. Ensure it's stopped, because + * VMMs otherwise steal CPU time just to pointlessly waggle + * the (masked) IRQ. + */ + clockevent_i8253_disable(); return false; - + } clockevent_i8253_init(true); global_clock_event =3D &i8253_clockevent; return true; diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index d4462fb26299..dfe6847fd99e 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include =20 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ @@ -1253,15 +1254,12 @@ static void __init check_system_tsc_reliable(void) * - TSC which does not stop in C-States * - the TSC_ADJUST register which allows to detect even minimal * modifications - * - not more than two sockets. As the number of sockets cannot be - * evaluated at the early boot stage where this has to be - * invoked, check the number of online memory nodes as a - * fallback solution which is an reasonable estimate. + * - not more than four packages */ if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && boot_cpu_has(X86_FEATURE_NONSTOP_TSC) && boot_cpu_has(X86_FEATURE_TSC_ADJUST) && - nr_online_nodes <=3D 4) + topology_max_packages() <=3D 4) tsc_disable_clocksource_watchdog(); } =20 @@ -1290,7 +1288,7 @@ int unsynchronized_tsc(void) */ if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { /* assume multi socket systems are not synchronized: */ - if (num_possible_cpus() > 1) + if (topology_max_packages() > 1) return 1; } =20 diff --git a/drivers/clocksource/i8253.c b/drivers/clocksource/i8253.c index d4350bb10b83..39f7c2d736d1 100644 --- a/drivers/clocksource/i8253.c +++ b/drivers/clocksource/i8253.c @@ -20,13 +20,6 @@ DEFINE_RAW_SPINLOCK(i8253_lock); EXPORT_SYMBOL(i8253_lock); =20 -/* - * Handle PIT quirk in pit_shutdown() where zeroing the counter register - * restarts the PIT, negating the shutdown. On platforms with the quirk, - * platform specific code can set this to false. - */ -bool i8253_clear_counter_on_shutdown __ro_after_init =3D true; - #ifdef CONFIG_CLKSRC_I8253 /* * Since the PIT overflows every tick, its not very useful @@ -108,21 +101,47 @@ int __init clocksource_i8253_init(void) #endif =20 #ifdef CONFIG_CLKEVT_I8253 -static int pit_shutdown(struct clock_event_device *evt) +void clockevent_i8253_disable(void) { - if (!clockevent_state_oneshot(evt) && !clockevent_state_periodic(evt)) - return 0; - raw_spin_lock(&i8253_lock); =20 + /* + * Writing the MODE register should stop the counter, according to + * the datasheet. This appears to work on real hardware (well, on + * modern Intel and AMD boxes; I didn't dig the Pegasos out of the + * shed). + * + * However, some virtual implementations differ, and the MODE change + * doesn't have any effect until either the counter is written (KVM + * in-kernel PIT) or the next interrupt (QEMU). And in those cases, + * it may not stop the *count*, only the interrupts. Although in + * the virt case, that probably doesn't matter, as the value of the + * counter will only be calculated on demand if the guest reads it; + * it's the interrupts which cause steal time. + * + * Hyper-V apparently has a bug where even in mode 0, the IRQ keeps + * firing repeatedly if the counter is running. But it *does* do the + * right thing when the MODE register is written. + * + * So: write the MODE and then load the counter, which ensures that + * the IRQ is stopped on those buggy virt implementations. And then + * write the MODE again, which is the right way to stop it. + */ outb_p(0x30, PIT_MODE); + outb_p(0, PIT_CH0); + outb_p(0, PIT_CH0); =20 - if (i8253_clear_counter_on_shutdown) { - outb_p(0, PIT_CH0); - outb_p(0, PIT_CH0); - } + outb_p(0x30, PIT_MODE); =20 raw_spin_unlock(&i8253_lock); +} + +static int pit_shutdown(struct clock_event_device *evt) +{ + if (!clockevent_state_oneshot(evt) && !clockevent_state_periodic(evt)) + return 0; + + clockevent_i8253_disable(); return 0; } =20 diff --git a/include/linux/i8253.h b/include/linux/i8253.h index 8336b2f6f834..56c280eb2d4f 100644 --- a/include/linux/i8253.h +++ b/include/linux/i8253.h @@ -21,9 +21,9 @@ #define PIT_LATCH ((PIT_TICK_RATE + HZ/2) / HZ) =20 extern raw_spinlock_t i8253_lock; -extern bool i8253_clear_counter_on_shutdown; extern struct clock_event_device i8253_clockevent; extern void clockevent_i8253_init(bool oneshot); +extern void clockevent_i8253_disable(void); =20 extern void setup_pit_timer(void); =20 . Subject: [GIT pull] x86/mm for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:15 +0200 (CEST) Linus, please pull the latest x86/mm branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-mm-2024-09-17 up to: 50c6dbdfd16e: x86/ioremap: Improve iounmap() address range checks Updates for x86 memory management: - Make LAM enablement safe vs. kernel threads using a process mm temporarily as switching back to the process would not update CR3 and therefore not enable LAM causing faults in user space when using tagged pointers. Cure it by synchronizing LAM enablement via IPIs to all CPUs which use the related mm. - Cure a LAM harmless inconsistency between CR3 and the state during context switch. It's both confusing and prone to lead to real bugs - Handle alt stack handling for threads which run with a non-zero protection key. The non-zero key prevents the kernel to access the alternate stack. Cure it by temporarily enabling all protection keys for the alternate stack setup/restore operations. - Provide a EFI config table identity mapping for kexec kernel to prevent kexec fails because the new kernel cannot access the config table array - Use GB pages only when a full GB is mapped in the identity map as otherwise the CPU can speculate into reserved areas after the end of memory which causes malfunction on UV systems. - Remove the noisy and pointless SRAT table dump during boot - Use is_ioremap_addr() for iounmap() address range checks instead of high_memory. is_ioremap_addr() is more precise. Thanks, tglx ------------------> Aruna Ramakrishna (4): x86/pkeys: Add PKRU as a parameter in signal handling functions x86/pkeys: Add helper functions to update PKRU on the sigframe x86/pkeys: Update PKRU to enable all pkeys before XSAVE x86/pkeys: Restore altstack access in sigreturn() Keith Lucas (1): selftests/mm: Add new testcases for pkeys Li RongQing (1): x86/mm: Don't print out SRAT table information Max Ramanouski (1): x86/ioremap: Improve iounmap() address range checks Steve Wahl (1): x86/mm/ident_map: Use gbpages only where full GB page should be mapped. Tao Liu (1): x86/kexec: Add EFI config table identity mapping for kexec kernel Yosry Ahmed (4): x86/mm: Use IPIs to synchronize LAM enablement x86/mm: Fix LAM inconsistency during context switch x86/mm: Cleanup prctl_enable_tagged_addr() nr_bits error checking x86/mm: Remove unused CR3_HW_ASID_BITS Yue Haibing (1): x86/mm: Remove unused NX related declarations Yuntao Wang (1): x86/mm: Remove duplicate check from build_cr3() arch/x86/include/asm/fpu/signal.h | 2 +- arch/x86/include/asm/mmu_context.h | 8 +- arch/x86/include/asm/pgtable_types.h | 2 - arch/x86/include/asm/tlbflush.h | 9 +- arch/x86/kernel/fpu/signal.c | 27 +- arch/x86/kernel/fpu/xstate.c | 13 + arch/x86/kernel/fpu/xstate.h | 2 + arch/x86/kernel/machine_kexec_64.c | 27 ++ arch/x86/kernel/process_64.c | 42 +- arch/x86/kernel/signal.c | 29 +- arch/x86/kernel/signal_64.c | 6 +- arch/x86/mm/ident_map.c | 23 +- arch/x86/mm/ioremap.c | 3 +- arch/x86/mm/srat.c | 6 +- arch/x86/mm/tlb.c | 19 +- include/linux/ioremap.h | 1 + tools/testing/selftests/mm/Makefile | 1 + tools/testing/selftests/mm/pkey-helpers.h | 13 +- tools/testing/selftests/mm/pkey_sighandler_tests.c | 481 +++++++++++++++++++= ++ tools/testing/selftests/mm/protection_keys.c | 10 - 20 files changed, 664 insertions(+), 60 deletions(-) create mode 100644 tools/testing/selftests/mm/pkey_sighandler_tests.c diff --git a/arch/x86/include/asm/fpu/signal.h b/arch/x86/include/asm/fpu/sig= nal.h index 611fa41711af..eccc75bc9c4f 100644 --- a/arch/x86/include/asm/fpu/signal.h +++ b/arch/x86/include/asm/fpu/signal.h @@ -29,7 +29,7 @@ fpu__alloc_mathframe(unsigned long sp, int ia32_frame, =20 unsigned long fpu__get_fpstate_size(void); =20 -extern bool copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int = size); +extern bool copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int = size, u32 pkru); extern void fpu__clear_user_states(struct fpu *fpu); extern bool fpu__restore_sig(void __user *buf, int ia32_frame); =20 diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_co= ntext.h index 8dac45a2c7fc..19091ebb8633 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -88,7 +88,13 @@ static inline void switch_ldt(struct mm_struct *prev, stru= ct mm_struct *next) #ifdef CONFIG_ADDRESS_MASKING static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm) { - return mm->context.lam_cr3_mask; + /* + * When switch_mm_irqs_off() is called for a kthread, it may race with + * LAM enablement. switch_mm_irqs_off() uses the LAM mask to do two + * things: populate CR3 and populate 'cpu_tlbstate.lam'. Make sure it + * reads a single value for both. + */ + return READ_ONCE(mm->context.lam_cr3_mask); } =20 static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgta= ble_types.h index 2f321137736c..6f82e75b6149 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -517,8 +517,6 @@ typedef struct page *pgtable_t; =20 extern pteval_t __supported_pte_mask; extern pteval_t __default_kernel_pte_mask; -extern void set_nx(void); -extern int nx_enabled; =20 #define pgprot_writecombine pgprot_writecombine extern pgprot_t pgprot_writecombine(pgprot_t prot); diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 25726893c6f4..69e79fff41b8 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -399,11 +399,10 @@ static inline u64 tlbstate_lam_cr3_mask(void) return lam << X86_CR3_LAM_U57_BIT; } =20 -static inline void set_tlbstate_lam_mode(struct mm_struct *mm) +static inline void cpu_tlbstate_update_lam(unsigned long lam, u64 untag_mask) { - this_cpu_write(cpu_tlbstate.lam, - mm->context.lam_cr3_mask >> X86_CR3_LAM_U57_BIT); - this_cpu_write(tlbstate_untag_mask, mm->context.untag_mask); + this_cpu_write(cpu_tlbstate.lam, lam >> X86_CR3_LAM_U57_BIT); + this_cpu_write(tlbstate_untag_mask, untag_mask); } =20 #else @@ -413,7 +412,7 @@ static inline u64 tlbstate_lam_cr3_mask(void) return 0; } =20 -static inline void set_tlbstate_lam_mode(struct mm_struct *mm) +static inline void cpu_tlbstate_update_lam(unsigned long lam, u64 untag_mask) { } #endif diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index 247f2225aa9f..1065ab995305 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -63,6 +63,16 @@ static inline bool check_xstate_in_sigframe(struct fxregs_= state __user *fxbuf, return true; } =20 +/* + * Update the value of PKRU register that was already pushed onto the signal= frame. + */ +static inline int update_pkru_in_sigframe(struct xregs_state __user *buf, u3= 2 pkru) +{ + if (unlikely(!cpu_feature_enabled(X86_FEATURE_OSPKE))) + return 0; + return __put_user(pkru, (unsigned int __user *)get_xsave_addr_user(buf, XFE= ATURE_PKRU)); +} + /* * Signal frame handlers. */ @@ -156,10 +166,17 @@ static inline bool save_xstate_epilog(void __user *buf,= int ia32_frame, return !err; } =20 -static inline int copy_fpregs_to_sigframe(struct xregs_state __user *buf) +static inline int copy_fpregs_to_sigframe(struct xregs_state __user *buf, u3= 2 pkru) { - if (use_xsave()) - return xsave_to_user_sigframe(buf); + int err =3D 0; + + if (use_xsave()) { + err =3D xsave_to_user_sigframe(buf); + if (!err) + err =3D update_pkru_in_sigframe(buf, pkru); + return err; + } + if (use_fxsr()) return fxsave_to_user_sigframe((struct fxregs_state __user *) buf); else @@ -185,7 +202,7 @@ static inline int copy_fpregs_to_sigframe(struct xregs_st= ate __user *buf) * For [f]xsave state, update the SW reserved fields in the [f]xsave frame * indicating the absence/presence of the extended state to the user. */ -bool copy_fpstate_to_sigframe(void __user *buf, void __user *buf_fx, int siz= e) +bool copy_fpstate_to_sigframe(void __user *buf, void __user *buf_fx, int siz= e, u32 pkru) { struct task_struct *tsk =3D current; struct fpstate *fpstate =3D tsk->thread.fpu.fpstate; @@ -228,7 +245,7 @@ bool copy_fpstate_to_sigframe(void __user *buf, void __us= er *buf_fx, int size) fpregs_restore_userregs(); =20 pagefault_disable(); - ret =3D copy_fpregs_to_sigframe(buf_fx); + ret =3D copy_fpregs_to_sigframe(buf_fx, pkru); pagefault_enable(); fpregs_unlock(); =20 diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index c5a026fee5e0..fa7628bb541b 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -993,6 +993,19 @@ void *get_xsave_addr(struct xregs_state *xsave, int xfea= ture_nr) } EXPORT_SYMBOL_GPL(get_xsave_addr); =20 +/* + * Given an xstate feature nr, calculate where in the xsave buffer the state= is. + * The xsave buffer should be in standard format, not compacted (e.g. user m= ode + * signal frames). + */ +void __user *get_xsave_addr_user(struct xregs_state __user *xsave, int xfeat= ure_nr) +{ + if (WARN_ON_ONCE(!xfeature_enabled(xfeature_nr))) + return NULL; + + return (void __user *)xsave + xstate_offsets[xfeature_nr]; +} + #ifdef CONFIG_ARCH_HAS_PKEYS =20 /* diff --git a/arch/x86/kernel/fpu/xstate.h b/arch/x86/kernel/fpu/xstate.h index 2ee0b9c53dcc..5f057e50df81 100644 --- a/arch/x86/kernel/fpu/xstate.h +++ b/arch/x86/kernel/fpu/xstate.h @@ -54,6 +54,8 @@ extern int copy_sigframe_from_user_to_xstate(struct task_st= ruct *tsk, const void extern void fpu__init_cpu_xstate(void); extern void fpu__init_system_xstate(unsigned int legacy_size); =20 +extern void __user *get_xsave_addr_user(struct xregs_state __user *xsave, in= t xfeature_nr); + static inline u64 xfeatures_mask_supervisor(void) { return fpu_kernel_cfg.max_features & XFEATURE_MASK_SUPERVISOR_SUPPORTED; diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kex= ec_64.c index cc0f7f70b17b..9c9ac606893e 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c @@ -28,6 +28,7 @@ #include #include #include +#include =20 #ifdef CONFIG_ACPI /* @@ -87,6 +88,8 @@ map_efi_systab(struct x86_mapping_info *info, pgd_t *level4= p) { #ifdef CONFIG_EFI unsigned long mstart, mend; + void *kaddr; + int ret; =20 if (!efi_enabled(EFI_BOOT)) return 0; @@ -102,6 +105,30 @@ map_efi_systab(struct x86_mapping_info *info, pgd_t *lev= el4p) if (!mstart) return 0; =20 + ret =3D kernel_ident_mapping_init(info, level4p, mstart, mend); + if (ret) + return ret; + + kaddr =3D memremap(mstart, mend - mstart, MEMREMAP_WB); + if (!kaddr) { + pr_err("Could not map UEFI system table\n"); + return -ENOMEM; + } + + mstart =3D efi_config_table; + + if (efi_enabled(EFI_64BIT)) { + efi_system_table_64_t *stbl =3D (efi_system_table_64_t *)kaddr; + + mend =3D mstart + sizeof(efi_config_table_64_t) * stbl->nr_tables; + } else { + efi_system_table_32_t *stbl =3D (efi_system_table_32_t *)kaddr; + + mend =3D mstart + sizeof(efi_config_table_32_t) * stbl->nr_tables; + } + + memunmap(kaddr); + return kernel_ident_mapping_init(info, level4p, mstart, mend); #endif return 0; diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 6d3d20e3e43a..226472332a70 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -798,6 +798,32 @@ static long prctl_map_vdso(const struct vdso_image *imag= e, unsigned long addr) =20 #define LAM_U57_BITS 6 =20 +static void enable_lam_func(void *__mm) +{ + struct mm_struct *mm =3D __mm; + unsigned long lam; + + if (this_cpu_read(cpu_tlbstate.loaded_mm) =3D=3D mm) { + lam =3D mm_lam_cr3_mask(mm); + write_cr3(__read_cr3() | lam); + cpu_tlbstate_update_lam(lam, mm_untag_mask(mm)); + } +} + +static void mm_enable_lam(struct mm_struct *mm) +{ + mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; + mm->context.untag_mask =3D ~GENMASK(62, 57); + + /* + * Even though the process must still be single-threaded at this + * point, kernel threads may be using the mm. IPI those kernel + * threads if they exist. + */ + on_each_cpu_mask(mm_cpumask(mm), enable_lam_func, mm, true); + set_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags); +} + static int prctl_enable_tagged_addr(struct mm_struct *mm, unsigned long nr_b= its) { if (!cpu_feature_enabled(X86_FEATURE_LAM)) @@ -814,25 +840,21 @@ static int prctl_enable_tagged_addr(struct mm_struct *m= m, unsigned long nr_bits) if (mmap_write_lock_killable(mm)) return -EINTR; =20 + /* + * MM_CONTEXT_LOCK_LAM is set on clone. Prevent LAM from + * being enabled unless the process is single threaded: + */ if (test_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags)) { mmap_write_unlock(mm); return -EBUSY; } =20 - if (!nr_bits) { - mmap_write_unlock(mm); - return -EINVAL; - } else if (nr_bits <=3D LAM_U57_BITS) { - mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; - mm->context.untag_mask =3D ~GENMASK(62, 57); - } else { + if (!nr_bits || nr_bits > LAM_U57_BITS) { mmap_write_unlock(mm); return -EINVAL; } =20 - write_cr3(__read_cr3() | mm->context.lam_cr3_mask); - set_tlbstate_lam_mode(mm); - set_bit(MM_CONTEXT_LOCK_LAM, &mm->context.flags); + mm_enable_lam(mm); =20 mmap_write_unlock(mm); =20 diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c index 31b6f5dddfc2..5f441039b572 100644 --- a/arch/x86/kernel/signal.c +++ b/arch/x86/kernel/signal.c @@ -60,6 +60,24 @@ static inline int is_x32_frame(struct ksignal *ksig) ksig->ka.sa.sa_flags & SA_X32_ABI; } =20 +/* + * Enable all pkeys temporarily, so as to ensure that both the current + * execution stack as well as the alternate signal stack are writeable. + * The application can use any of the available pkeys to protect the + * alternate signal stack, and we don't know which one it is, so enable + * all. The PKRU register will be reset to init_pkru later in the flow, + * in fpu__clear_user_states(), and it is the application's responsibility + * to enable the appropriate pkey as the first step in the signal handler + * so that the handler does not segfault. + */ +static inline u32 sig_prepare_pkru(void) +{ + u32 orig_pkru =3D read_pkru(); + + write_pkru(0); + return orig_pkru; +} + /* * Set up a signal frame. */ @@ -84,6 +102,7 @@ get_sigframe(struct ksignal *ksig, struct pt_regs *regs, s= ize_t frame_size, unsigned long math_size =3D 0; unsigned long sp =3D regs->sp; unsigned long buf_fx =3D 0; + u32 pkru; =20 /* redzone */ if (!ia32_frame) @@ -138,9 +157,17 @@ get_sigframe(struct ksignal *ksig, struct pt_regs *regs,= size_t frame_size, return (void __user *)-1L; } =20 + /* Update PKRU to enable access to the alternate signal stack. */ + pkru =3D sig_prepare_pkru(); /* save i387 and extended state */ - if (!copy_fpstate_to_sigframe(*fpstate, (void __user *)buf_fx, math_size)) + if (!copy_fpstate_to_sigframe(*fpstate, (void __user *)buf_fx, math_size, p= kru)) { + /* + * Restore PKRU to the original, user-defined value; disable + * extra pkeys enabled for the alternate signal stack, if any. + */ + write_pkru(pkru); return (void __user *)-1L; + } =20 return (void __user *)sp; } diff --git a/arch/x86/kernel/signal_64.c b/arch/x86/kernel/signal_64.c index 8a94053c5444..ee9453891901 100644 --- a/arch/x86/kernel/signal_64.c +++ b/arch/x86/kernel/signal_64.c @@ -260,13 +260,13 @@ SYSCALL_DEFINE0(rt_sigreturn) =20 set_current_blocked(&set); =20 - if (!restore_sigcontext(regs, &frame->uc.uc_mcontext, uc_flags)) + if (restore_altstack(&frame->uc.uc_stack)) goto badframe; =20 - if (restore_signal_shadow_stack()) + if (!restore_sigcontext(regs, &frame->uc.uc_mcontext, uc_flags)) goto badframe; =20 - if (restore_altstack(&frame->uc.uc_stack)) + if (restore_signal_shadow_stack()) goto badframe; =20 return regs->ax; diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c index c45127265f2f..437e96fb4977 100644 --- a/arch/x86/mm/ident_map.c +++ b/arch/x86/mm/ident_map.c @@ -99,18 +99,31 @@ static int ident_pud_init(struct x86_mapping_info *info, = pud_t *pud_page, for (; addr < end; addr =3D next) { pud_t *pud =3D pud_page + pud_index(addr); pmd_t *pmd; + bool use_gbpage; =20 next =3D (addr & PUD_MASK) + PUD_SIZE; if (next > end) next =3D end; =20 - if (info->direct_gbpages) { - pud_t pudval; + /* if this is already a gbpage, this portion is already mapped */ + if (pud_leaf(*pud)) + continue; + + /* Is using a gbpage allowed? */ + use_gbpage =3D info->direct_gbpages; =20 - if (pud_present(*pud)) - continue; + /* Don't use gbpage if it maps more than the requested region. */ + /* at the begining: */ + use_gbpage &=3D ((addr & ~PUD_MASK) =3D=3D 0); + /* ... or at the end: */ + use_gbpage &=3D ((next & ~PUD_MASK) =3D=3D 0); + + /* Never overwrite existing mappings */ + use_gbpage &=3D !pud_present(*pud); + + if (use_gbpage) { + pud_t pudval; =20 - addr &=3D PUD_MASK; pudval =3D __pud((addr - info->offset) | info->page_flag); set_pud(pud, pudval); continue; diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index aa7d279321ea..70b02fc61d93 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -457,7 +458,7 @@ void iounmap(volatile void __iomem *addr) { struct vm_struct *p, *o; =20 - if ((void __force *)addr <=3D high_memory) + if (WARN_ON_ONCE(!is_ioremap_addr((void __force *)addr))) return; =20 /* diff --git a/arch/x86/mm/srat.c b/arch/x86/mm/srat.c index 9c52a95937ad..6f8e0f21c710 100644 --- a/arch/x86/mm/srat.c +++ b/arch/x86/mm/srat.c @@ -57,8 +57,7 @@ acpi_numa_x2apic_affinity_init(struct acpi_srat_x2apic_cpu_= affinity *pa) } set_apicid_to_node(apic_id, node); node_set(node, numa_nodes_parsed); - printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%04x -> Node %u\n", - pxm, apic_id, node); + pr_debug("SRAT: PXM %u -> APIC 0x%04x -> Node %u\n", pxm, apic_id, node); } =20 /* Callback for Proximity Domain -> LAPIC mapping */ @@ -98,8 +97,7 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affi= nity *pa) =20 set_apicid_to_node(apic_id, node); node_set(node, numa_nodes_parsed); - printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%02x -> Node %u\n", - pxm, apic_id, node); + pr_debug("SRAT: PXM %u -> APIC 0x%02x -> Node %u\n", pxm, apic_id, node); } =20 int __init x86_acpi_numa_init(void) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 44ac64f3a047..86593d1b787d 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include #include @@ -85,9 +86,6 @@ * */ =20 -/* There are 12 bits of space for ASIDS in CR3 */ -#define CR3_HW_ASID_BITS 12 - /* * When enabled, MITIGATION_PAGE_TABLE_ISOLATION consumes a single bit for * user/kernel switches @@ -160,7 +158,6 @@ static inline unsigned long build_cr3(pgd_t *pgd, u16 asi= d, unsigned long lam) unsigned long cr3 =3D __sme_pa(pgd) | lam; =20 if (static_cpu_has(X86_FEATURE_PCID)) { - VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); cr3 |=3D kern_pcid(asid); } else { VM_WARN_ON_ONCE(asid !=3D 0); @@ -503,9 +500,9 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct = mm_struct *next, { struct mm_struct *prev =3D this_cpu_read(cpu_tlbstate.loaded_mm); u16 prev_asid =3D this_cpu_read(cpu_tlbstate.loaded_mm_asid); - unsigned long new_lam =3D mm_lam_cr3_mask(next); bool was_lazy =3D this_cpu_read(cpu_tlbstate_shared.is_lazy); unsigned cpu =3D smp_processor_id(); + unsigned long new_lam; u64 next_tlb_gen; bool need_flush; u16 new_asid; @@ -619,9 +616,7 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct = mm_struct *next, cpumask_clear_cpu(cpu, mm_cpumask(prev)); } =20 - /* - * Start remote flushes and then read tlb_gen. - */ + /* Start receiving IPIs and then read tlb_gen (and LAM below) */ if (next !=3D &init_mm) cpumask_set_cpu(cpu, mm_cpumask(next)); next_tlb_gen =3D atomic64_read(&next->context.tlb_gen); @@ -633,7 +628,7 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct = mm_struct *next, barrier(); } =20 - set_tlbstate_lam_mode(next); + new_lam =3D mm_lam_cr3_mask(next); if (need_flush) { this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); @@ -652,6 +647,7 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct = mm_struct *next, =20 this_cpu_write(cpu_tlbstate.loaded_mm, next); this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid); + cpu_tlbstate_update_lam(new_lam, mm_untag_mask(next)); =20 if (next !=3D prev) { cr4_update_pce_mm(next); @@ -698,6 +694,7 @@ void initialize_tlbstate_and_flush(void) int i; struct mm_struct *mm =3D this_cpu_read(cpu_tlbstate.loaded_mm); u64 tlb_gen =3D atomic64_read(&init_mm.context.tlb_gen); + unsigned long lam =3D mm_lam_cr3_mask(mm); unsigned long cr3 =3D __read_cr3(); =20 /* Assert that CR3 already references the right mm. */ @@ -705,7 +702,7 @@ void initialize_tlbstate_and_flush(void) =20 /* LAM expected to be disabled */ WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)); - WARN_ON(mm_lam_cr3_mask(mm)); + WARN_ON(lam); =20 /* * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization @@ -724,7 +721,7 @@ void initialize_tlbstate_and_flush(void) this_cpu_write(cpu_tlbstate.next_asid, 1); this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen); - set_tlbstate_lam_mode(mm); + cpu_tlbstate_update_lam(lam, mm_untag_mask(mm)); =20 for (i =3D 1; i < TLB_NR_DYN_ASIDS; i++) this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0); diff --git a/include/linux/ioremap.h b/include/linux/ioremap.h index f0e99fc7dd8b..2bd1661fe9ad 100644 --- a/include/linux/ioremap.h +++ b/include/linux/ioremap.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #if defined(CONFIG_HAS_IOMEM) || defined(CONFIG_GENERIC_IOREMAP) /* diff --git a/tools/testing/selftests/mm/Makefile b/tools/testing/selftests/mm= /Makefile index 901e0d07765b..1f176fff7054 100644 --- a/tools/testing/selftests/mm/Makefile +++ b/tools/testing/selftests/mm/Makefile @@ -88,6 +88,7 @@ CAN_BUILD_X86_64 :=3D $(shell ./../x86/check_cc.sh "$(CC)" = ../x86/trivial_64bit_pr CAN_BUILD_WITH_NOPIE :=3D $(shell ./../x86/check_cc.sh "$(CC)" ../x86/trivia= l_program.c -no-pie) =20 VMTARGETS :=3D protection_keys +VMTARGETS +=3D pkey_sighandler_tests BINARIES_32 :=3D $(VMTARGETS:%=3D%_32) BINARIES_64 :=3D $(VMTARGETS:%=3D%_64) =20 diff --git a/tools/testing/selftests/mm/pkey-helpers.h b/tools/testing/selfte= sts/mm/pkey-helpers.h index 1af3156a9db8..4d31a309a46b 100644 --- a/tools/testing/selftests/mm/pkey-helpers.h +++ b/tools/testing/selftests/mm/pkey-helpers.h @@ -79,7 +79,18 @@ extern void abort_hooks(void); } \ } while (0) =20 -__attribute__((noinline)) int read_ptr(int *ptr); +#define barrier() __asm__ __volatile__("": : :"memory") +#ifndef noinline +# define noinline __attribute__((noinline)) +#endif + +noinline int read_ptr(int *ptr) +{ + /* Keep GCC from optimizing this away somehow */ + barrier(); + return *ptr; +} + void expected_pkey_fault(int pkey); int sys_pkey_alloc(unsigned long flags, unsigned long init_val); int sys_pkey_free(unsigned long pkey); diff --git a/tools/testing/selftests/mm/pkey_sighandler_tests.c b/tools/testi= ng/selftests/mm/pkey_sighandler_tests.c new file mode 100644 index 000000000000..a8088b645ad6 --- /dev/null +++ b/tools/testing/selftests/mm/pkey_sighandler_tests.c @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tests Memory Protection Keys (see Documentation/core-api/protection-keys.= rst) + * + * The testcases in this file exercise various flows related to signal handl= ing, + * using an alternate signal stack, with the default pkey (pkey 0) disabled. + * + * Compile with: + * gcc -mxsave -o pkey_sighandler_tests -O2 -g -std=3Dgnu99 -pthread -W= all pkey_sighandler_tests.c -I../../../../tools/include -lrt -ldl -lm + * gcc -mxsave -m32 -o pkey_sighandler_tests -O2 -g -std=3Dgnu99 -pthread -W= all pkey_sighandler_tests.c -I../../../../tools/include -lrt -ldl -lm + */ +#define _GNU_SOURCE +#define __SANE_USERSPACE_TYPES__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pkey-helpers.h" + +#define STACK_SIZE PTHREAD_STACK_MIN + +void expected_pkey_fault(int pkey) {} + +pthread_mutex_t mutex =3D PTHREAD_MUTEX_INITIALIZER; +pthread_cond_t cond =3D PTHREAD_COND_INITIALIZER; +siginfo_t siginfo =3D {0}; + +/* + * We need to use inline assembly instead of glibc's syscall because glibc's + * syscall will attempt to access the PLT in order to call a library function + * which is protected by MPK 0 which we don't have access to. + */ +static inline __always_inline +long syscall_raw(long n, long a1, long a2, long a3, long a4, long a5, long a= 6) +{ + unsigned long ret; +#ifdef __x86_64__ + register long r10 asm("r10") =3D a4; + register long r8 asm("r8") =3D a5; + register long r9 asm("r9") =3D a6; + asm volatile ("syscall" + : "=3Da"(ret) + : "a"(n), "D"(a1), "S"(a2), "d"(a3), "r"(r10), "r"(r8), "r"(r9) + : "rcx", "r11", "memory"); +#elif defined __i386__ + asm volatile ("int $0x80" + : "=3Da"(ret) + : "a"(n), "b"(a1), "c"(a2), "d"(a3), "S"(a4), "D"(a5) + : "memory"); +#else +# error syscall_raw() not implemented +#endif + return ret; +} + +static void sigsegv_handler(int signo, siginfo_t *info, void *ucontext) +{ + pthread_mutex_lock(&mutex); + + memcpy(&siginfo, info, sizeof(siginfo_t)); + + pthread_cond_signal(&cond); + pthread_mutex_unlock(&mutex); + + syscall_raw(SYS_exit, 0, 0, 0, 0, 0, 0); +} + +static void sigusr1_handler(int signo, siginfo_t *info, void *ucontext) +{ + pthread_mutex_lock(&mutex); + + memcpy(&siginfo, info, sizeof(siginfo_t)); + + pthread_cond_signal(&cond); + pthread_mutex_unlock(&mutex); +} + +static void sigusr2_handler(int signo, siginfo_t *info, void *ucontext) +{ + /* + * pkru should be the init_pkru value which enabled MPK 0 so + * we can use library functions. + */ + printf("%s invoked.\n", __func__); +} + +static void raise_sigusr2(void) +{ + pid_t tid =3D 0; + + tid =3D syscall_raw(SYS_gettid, 0, 0, 0, 0, 0, 0); + + syscall_raw(SYS_tkill, tid, SIGUSR2, 0, 0, 0, 0); + + /* + * We should return from the signal handler here and be able to + * return to the interrupted thread. + */ +} + +static void *thread_segv_with_pkey0_disabled(void *ptr) +{ + /* Disable MPK 0 (and all others too) */ + __write_pkey_reg(0x55555555); + + /* Segfault (with SEGV_MAPERR) */ + *(int *) (0x1) =3D 1; + return NULL; +} + +static void *thread_segv_pkuerr_stack(void *ptr) +{ + /* Disable MPK 0 (and all others too) */ + __write_pkey_reg(0x55555555); + + /* After we disable MPK 0, we can't access the stack to return */ + return NULL; +} + +static void *thread_segv_maperr_ptr(void *ptr) +{ + stack_t *stack =3D ptr; + int *bad =3D (int *)1; + + /* + * Setup alternate signal stack, which should be pkey_mprotect()ed by + * MPK 0. The thread's stack cannot be used for signals because it is + * not accessible by the default init_pkru value of 0x55555554. + */ + syscall_raw(SYS_sigaltstack, (long)stack, 0, 0, 0, 0, 0); + + /* Disable MPK 0. Only MPK 1 is enabled. */ + __write_pkey_reg(0x55555551); + + /* Segfault */ + *bad =3D 1; + syscall_raw(SYS_exit, 0, 0, 0, 0, 0, 0); + return NULL; +} + +/* + * Verify that the sigsegv handler is invoked when pkey 0 is disabled. + * Note that the new thread stack and the alternate signal stack is + * protected by MPK 0. + */ +static void test_sigsegv_handler_with_pkey0_disabled(void) +{ + struct sigaction sa; + pthread_attr_t attr; + pthread_t thr; + + sa.sa_flags =3D SA_SIGINFO; + + sa.sa_sigaction =3D sigsegv_handler; + sigemptyset(&sa.sa_mask); + if (sigaction(SIGSEGV, &sa, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + memset(&siginfo, 0, sizeof(siginfo)); + + pthread_attr_init(&attr); + pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); + + pthread_create(&thr, &attr, thread_segv_with_pkey0_disabled, NULL); + + pthread_mutex_lock(&mutex); + while (siginfo.si_signo =3D=3D 0) + pthread_cond_wait(&cond, &mutex); + pthread_mutex_unlock(&mutex); + + ksft_test_result(siginfo.si_signo =3D=3D SIGSEGV && + siginfo.si_code =3D=3D SEGV_MAPERR && + siginfo.si_addr =3D=3D (void *)1, + "%s\n", __func__); +} + +/* + * Verify that the sigsegv handler is invoked when pkey 0 is disabled. + * Note that the new thread stack and the alternate signal stack is + * protected by MPK 0, which renders them inaccessible when MPK 0 + * is disabled. So just the return from the thread should cause a + * segfault with SEGV_PKUERR. + */ +static void test_sigsegv_handler_cannot_access_stack(void) +{ + struct sigaction sa; + pthread_attr_t attr; + pthread_t thr; + + sa.sa_flags =3D SA_SIGINFO; + + sa.sa_sigaction =3D sigsegv_handler; + sigemptyset(&sa.sa_mask); + if (sigaction(SIGSEGV, &sa, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + memset(&siginfo, 0, sizeof(siginfo)); + + pthread_attr_init(&attr); + pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); + + pthread_create(&thr, &attr, thread_segv_pkuerr_stack, NULL); + + pthread_mutex_lock(&mutex); + while (siginfo.si_signo =3D=3D 0) + pthread_cond_wait(&cond, &mutex); + pthread_mutex_unlock(&mutex); + + ksft_test_result(siginfo.si_signo =3D=3D SIGSEGV && + siginfo.si_code =3D=3D SEGV_PKUERR, + "%s\n", __func__); +} + +/* + * Verify that the sigsegv handler that uses an alternate signal stack + * is correctly invoked for a thread which uses a non-zero MPK to protect + * its own stack, and disables all other MPKs (including 0). + */ +static void test_sigsegv_handler_with_different_pkey_for_stack(void) +{ + struct sigaction sa; + static stack_t sigstack; + void *stack; + int pkey; + int parent_pid =3D 0; + int child_pid =3D 0; + + sa.sa_flags =3D SA_SIGINFO | SA_ONSTACK; + + sa.sa_sigaction =3D sigsegv_handler; + + sigemptyset(&sa.sa_mask); + if (sigaction(SIGSEGV, &sa, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + stack =3D mmap(0, STACK_SIZE, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + + assert(stack !=3D MAP_FAILED); + + /* Allow access to MPK 0 and MPK 1 */ + __write_pkey_reg(0x55555550); + + /* Protect the new stack with MPK 1 */ + pkey =3D pkey_alloc(0, 0); + pkey_mprotect(stack, STACK_SIZE, PROT_READ | PROT_WRITE, pkey); + + /* Set up alternate signal stack that will use the default MPK */ + sigstack.ss_sp =3D mmap(0, STACK_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + sigstack.ss_flags =3D 0; + sigstack.ss_size =3D STACK_SIZE; + + memset(&siginfo, 0, sizeof(siginfo)); + + /* Use clone to avoid newer glibcs using rseq on new threads */ + long ret =3D syscall_raw(SYS_clone, + CLONE_VM | CLONE_FS | CLONE_FILES | + CLONE_SIGHAND | CLONE_THREAD | CLONE_SYSVSEM | + CLONE_PARENT_SETTID | CLONE_CHILD_CLEARTID | + CLONE_DETACHED, + (long) ((char *)(stack) + STACK_SIZE), + (long) &parent_pid, + (long) &child_pid, 0, 0); + + if (ret < 0) { + errno =3D -ret; + perror("clone"); + } else if (ret =3D=3D 0) { + thread_segv_maperr_ptr(&sigstack); + syscall_raw(SYS_exit, 0, 0, 0, 0, 0, 0); + } + + pthread_mutex_lock(&mutex); + while (siginfo.si_signo =3D=3D 0) + pthread_cond_wait(&cond, &mutex); + pthread_mutex_unlock(&mutex); + + ksft_test_result(siginfo.si_signo =3D=3D SIGSEGV && + siginfo.si_code =3D=3D SEGV_MAPERR && + siginfo.si_addr =3D=3D (void *)1, + "%s\n", __func__); +} + +/* + * Verify that the PKRU value set by the application is correctly + * restored upon return from signal handling. + */ +static void test_pkru_preserved_after_sigusr1(void) +{ + struct sigaction sa; + unsigned long pkru =3D 0x45454544; + + sa.sa_flags =3D SA_SIGINFO; + + sa.sa_sigaction =3D sigusr1_handler; + sigemptyset(&sa.sa_mask); + if (sigaction(SIGUSR1, &sa, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + memset(&siginfo, 0, sizeof(siginfo)); + + __write_pkey_reg(pkru); + + raise(SIGUSR1); + + pthread_mutex_lock(&mutex); + while (siginfo.si_signo =3D=3D 0) + pthread_cond_wait(&cond, &mutex); + pthread_mutex_unlock(&mutex); + + /* Ensure the pkru value is the same after returning from signal. */ + ksft_test_result(pkru =3D=3D __read_pkey_reg() && + siginfo.si_signo =3D=3D SIGUSR1, + "%s\n", __func__); +} + +static noinline void *thread_sigusr2_self(void *ptr) +{ + /* + * A const char array like "Resuming after SIGUSR2" won't be stored on + * the stack and the code could access it via an offset from the program + * counter. This makes sure it's on the function's stack frame. + */ + char str[] =3D {'R', 'e', 's', 'u', 'm', 'i', 'n', 'g', ' ', + 'a', 'f', 't', 'e', 'r', ' ', + 'S', 'I', 'G', 'U', 'S', 'R', '2', + '.', '.', '.', '\n', '\0'}; + stack_t *stack =3D ptr; + + /* + * Setup alternate signal stack, which should be pkey_mprotect()ed by + * MPK 0. The thread's stack cannot be used for signals because it is + * not accessible by the default init_pkru value of 0x55555554. + */ + syscall(SYS_sigaltstack, (long)stack, 0, 0, 0, 0, 0); + + /* Disable MPK 0. Only MPK 2 is enabled. */ + __write_pkey_reg(0x55555545); + + raise_sigusr2(); + + /* Do something, to show the thread resumed execution after the signal */ + syscall_raw(SYS_write, 1, (long) str, sizeof(str) - 1, 0, 0, 0); + + /* + * We can't return to test_pkru_sigreturn because it + * will attempt to use a %rbp value which is on the stack + * of the main thread. + */ + syscall_raw(SYS_exit, 0, 0, 0, 0, 0, 0); + return NULL; +} + +/* + * Verify that sigreturn is able to restore altstack even if the thread had + * disabled pkey 0. + */ +static void test_pkru_sigreturn(void) +{ + struct sigaction sa =3D {0}; + static stack_t sigstack; + void *stack; + int pkey; + int parent_pid =3D 0; + int child_pid =3D 0; + + sa.sa_handler =3D SIG_DFL; + sa.sa_flags =3D 0; + sigemptyset(&sa.sa_mask); + + /* + * For this testcase, we do not want to handle SIGSEGV. Reset handler + * to default so that the application can crash if it receives SIGSEGV. + */ + if (sigaction(SIGSEGV, &sa, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + sa.sa_flags =3D SA_SIGINFO | SA_ONSTACK; + sa.sa_sigaction =3D sigusr2_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGUSR2, &sa, NULL) =3D=3D -1) { + perror("sigaction"); + exit(EXIT_FAILURE); + } + + stack =3D mmap(0, STACK_SIZE, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + + assert(stack !=3D MAP_FAILED); + + /* + * Allow access to MPK 0 and MPK 2. The child thread (to be created + * later in this flow) will have its stack protected by MPK 2, whereas + * the current thread's stack is protected by the default MPK 0. Hence + * both need to be enabled. + */ + __write_pkey_reg(0x55555544); + + /* Protect the stack with MPK 2 */ + pkey =3D pkey_alloc(0, 0); + pkey_mprotect(stack, STACK_SIZE, PROT_READ | PROT_WRITE, pkey); + + /* Set up alternate signal stack that will use the default MPK */ + sigstack.ss_sp =3D mmap(0, STACK_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + sigstack.ss_flags =3D 0; + sigstack.ss_size =3D STACK_SIZE; + + /* Use clone to avoid newer glibcs using rseq on new threads */ + long ret =3D syscall_raw(SYS_clone, + CLONE_VM | CLONE_FS | CLONE_FILES | + CLONE_SIGHAND | CLONE_THREAD | CLONE_SYSVSEM | + CLONE_PARENT_SETTID | CLONE_CHILD_CLEARTID | + CLONE_DETACHED, + (long) ((char *)(stack) + STACK_SIZE), + (long) &parent_pid, + (long) &child_pid, 0, 0); + + if (ret < 0) { + errno =3D -ret; + perror("clone"); + } else if (ret =3D=3D 0) { + thread_sigusr2_self(&sigstack); + syscall_raw(SYS_exit, 0, 0, 0, 0, 0, 0); + } + + child_pid =3D ret; + /* Check that thread exited */ + do { + sched_yield(); + ret =3D syscall_raw(SYS_tkill, child_pid, 0, 0, 0, 0, 0); + } while (ret !=3D -ESRCH && ret !=3D -EINVAL); + + ksft_test_result_pass("%s\n", __func__); +} + +static void (*pkey_tests[])(void) =3D { + test_sigsegv_handler_with_pkey0_disabled, + test_sigsegv_handler_cannot_access_stack, + test_sigsegv_handler_with_different_pkey_for_stack, + test_pkru_preserved_after_sigusr1, + test_pkru_sigreturn +}; + +int main(int argc, char *argv[]) +{ + int i; + + ksft_print_header(); + ksft_set_plan(ARRAY_SIZE(pkey_tests)); + + for (i =3D 0; i < ARRAY_SIZE(pkey_tests); i++) + (*pkey_tests[i])(); + + ksft_finished(); + return 0; +} diff --git a/tools/testing/selftests/mm/protection_keys.c b/tools/testing/sel= ftests/mm/protection_keys.c index eaa6d1fc5328..cc6de1644360 100644 --- a/tools/testing/selftests/mm/protection_keys.c +++ b/tools/testing/selftests/mm/protection_keys.c @@ -950,16 +950,6 @@ void close_test_fds(void) nr_test_fds =3D 0; } =20 -#define barrier() __asm__ __volatile__("": : :"memory") -__attribute__((noinline)) int read_ptr(int *ptr) -{ - /* - * Keep GCC from optimizing this away somehow - */ - barrier(); - return *ptr; -} - void test_pkey_alloc_free_attach_pkey0(int *ptr, u16 pkey) { int i, err; . Subject: [GIT pull] x86/apic for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:04 +0200 (CEST) Linus, please pull the latest x86/apic branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-apic-2024-09= -17 up to: a1fab3e69d9d: x86/irq: Fix comment on IRQ vector layout Updates for the x86 APIC code: - Handle an allocation failure in the IO/APIC code gracefully instead of crashing the machine. - Remove support for APIC local destination mode on 64bit Logical destination mode of the local APIC is used for systems with up to 8 CPUs. It has an advantage over physical destination mode as it allows to target multiple CPUs at once with IPIs. That advantage was definitely worth it when systems with up to 8 CPUs were state of the art for servers and workstations, but that's history. In the recent past there were quite some reports of new laptops failing to boot with logical destination mode, but they work fine with physical destination mode. That's not a suprise because physical destination mode is guaranteed to work as it's the only way to get a CPU up and running via the INIT/INIT/STARTUP sequence. Some of the affected systems were cured by BIOS updates, but not all OEMs provide them. As the number of CPUs keep increasing, logical destination mode becomes less used and the benefit for small systems, like laptops, is not really worth the trouble. So just remove logical destination mode support for 64bit and be done with it. - Code and comment cleanups in the APIC area. Thanks, tglx ------------------> Sohil Mehta (1): x86/irq: Fix comment on IRQ vector layout Thomas Gleixner (16): x86/ioapic: Handle allocation failures gracefully x86/ioapic: Mark mp_alloc_timer_irq() __init x86/ioapic: Cleanup structs x86/ioapic: Use guard() for locking where applicable x86/apic: Provide apic_printk() helpers x86/apic: Cleanup apic_printk()s x86/ioapic: Cleanup apic_printk()s x86/ioapic: Cleanup guarded debug printk()s x86/mpparse: Cleanup apic_printk()s iommu/vt-d: Cleanup apic_printk() x86/ioapic: Move replace_pin_at_irq_node() to the call site x86/ioapic: Cleanup comments x86/ioapic: Cleanup bracket usage x86/ioapic: Cleanup line breaks x86/ioapic: Cleanup remaining coding style issues x86/apic: Remove logical destination mode for 64-bit Yue Haibing (2): x86/apic: Remove unused inline function apic_set_eoi_cb() x86/apic: Remove unused extern declarations arch/x86/include/asm/apic.h | 48 +-- arch/x86/include/asm/irq_vectors.h | 4 +- arch/x86/kernel/apic/apic.c | 81 ++-- arch/x86/kernel/apic/apic_flat_64.c | 119 +----- arch/x86/kernel/apic/io_apic.c | 749 +++++++++++++++-------------------= -- arch/x86/kernel/mpparse.c | 13 +- drivers/iommu/intel/irq_remapping.c | 11 +- 7 files changed, 378 insertions(+), 647 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9327eb00e96d..f21ff1932699 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -18,6 +18,11 @@ =20 #define ARCH_APICTIMER_STOPS_ON_C3 1 =20 +/* Macros for apic_extnmi which controls external NMI masking */ +#define APIC_EXTNMI_BSP 0 /* Default */ +#define APIC_EXTNMI_ALL 1 +#define APIC_EXTNMI_NONE 2 + /* * Debugging macros */ @@ -25,22 +30,22 @@ #define APIC_VERBOSE 1 #define APIC_DEBUG 2 =20 -/* Macros for apic_extnmi which controls external NMI masking */ -#define APIC_EXTNMI_BSP 0 /* Default */ -#define APIC_EXTNMI_ALL 1 -#define APIC_EXTNMI_NONE 2 - /* - * Define the default level of output to be very little - * This can be turned up by using apic=3Dverbose for more - * information and apic=3Ddebug for _lots_ of information. - * apic_verbosity is defined in apic.c + * Define the default level of output to be very little This can be turned + * up by using apic=3Dverbose for more information and apic=3Ddebug for _lot= s_ + * of information. apic_verbosity is defined in apic.c */ -#define apic_printk(v, s, a...) do { \ - if ((v) <=3D apic_verbosity) \ - printk(s, ##a); \ - } while (0) - +#define apic_printk(v, s, a...) \ +do { \ + if ((v) <=3D apic_verbosity) \ + printk(s, ##a); \ +} while (0) + +#define apic_pr_verbose(s, a...) apic_printk(APIC_VERBOSE, KERN_INFO s, ##a) +#define apic_pr_debug(s, a...) apic_printk(APIC_DEBUG, KERN_DEBUG s, ##a) +#define apic_pr_debug_cont(s, a...) apic_printk(APIC_DEBUG, KERN_CONT s, ##a) +/* Unconditional debug prints for code which is guarded by apic_verbosity al= ready */ +#define apic_dbg(s, a...) printk(KERN_DEBUG s, ##a) =20 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) extern void x86_32_probe_apic(void); @@ -122,8 +127,6 @@ static inline bool apic_is_x2apic_enabled(void) =20 extern void enable_IR_x2apic(void); =20 -extern int get_physical_broadcast(void); - extern int lapic_get_maxlvt(void); extern void clear_local_APIC(void); extern void disconnect_bsp_APIC(int virt_wire_setup); @@ -345,20 +348,12 @@ extern struct apic *apic; * APIC drivers are probed based on how they are listed in the .apicdrivers * section. So the order is important and enforced by the ordering * of different apic driver files in the Makefile. - * - * For the files having two apic drivers, we use apic_drivers() - * to enforce the order with in them. */ #define apic_driver(sym) \ static const struct apic *__apicdrivers_##sym __used \ __aligned(sizeof(struct apic *)) \ __section(".apicdrivers") =3D { &sym } =20 -#define apic_drivers(sym1, sym2) \ - static struct apic *__apicdrivers_##sym1##sym2[2] __used \ - __aligned(sizeof(struct apic *)) \ - __section(".apicdrivers") =3D { &sym1, &sym2 } - extern struct apic *__apicdrivers[], *__apicdrivers_end[]; =20 /* @@ -484,7 +479,6 @@ static inline u64 apic_icr_read(void) { return 0; } static inline void apic_icr_write(u32 low, u32 high) { } static inline void apic_wait_icr_idle(void) { } static inline u32 safe_apic_wait_icr_idle(void) { return 0; } -static inline void apic_set_eoi_cb(void (*eoi)(void)) {} static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } static inline void apic_setup_apic_calls(void) { } =20 @@ -512,8 +506,6 @@ static inline bool is_vector_pending(unsigned int vector) #define TRAMPOLINE_PHYS_LOW 0x467 #define TRAMPOLINE_PHYS_HIGH 0x469 =20 -extern void generic_bigsmp_probe(void); - #ifdef CONFIG_X86_LOCAL_APIC =20 #include @@ -536,8 +528,6 @@ static inline int default_acpi_madt_oem_check(char *a, ch= ar *b) { return 0; } static inline void x86_64_probe_apic(void) { } #endif =20 -extern int default_apic_id_valid(u32 apicid); - extern u32 apic_default_calc_apicid(unsigned int cpu); extern u32 apic_flat_calc_apicid(unsigned int cpu); =20 diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_ve= ctors.h index 13aea8fc3d45..47051871b436 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h @@ -18,8 +18,8 @@ * Vectors 0 ... 31 : system traps and exceptions - hardcoded events * Vectors 32 ... 127 : device interrupts * Vector 128 : legacy int80 syscall interface - * Vectors 129 ... LOCAL_TIMER_VECTOR-1 - * Vectors LOCAL_TIMER_VECTOR ... 255 : special interrupts + * Vectors 129 ... FIRST_SYSTEM_VECTOR-1 : device interrupts + * Vectors FIRST_SYSTEM_VECTOR ... 255 : special interrupts * * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. * diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 66fd4b2a37a3..1838a73b0950 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -677,7 +677,7 @@ calibrate_by_pmtimer(u32 deltapm, long *delta, long *delt= atsc) return -1; #endif =20 - apic_printk(APIC_VERBOSE, "... PM-Timer delta =3D %u\n", deltapm); + apic_pr_verbose("... PM-Timer delta =3D %u\n", deltapm); =20 /* Check, if the PM timer is available */ if (!deltapm) @@ -687,14 +687,14 @@ calibrate_by_pmtimer(u32 deltapm, long *delta, long *de= ltatsc) =20 if (deltapm > (pm_100ms - pm_thresh) && deltapm < (pm_100ms + pm_thresh)) { - apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); + apic_pr_verbose("... PM-Timer result ok\n"); return 0; } =20 res =3D (((u64)deltapm) * mult) >> 22; do_div(res, 1000000); - pr_warn("APIC calibration not consistent " - "with PM-Timer: %ldms instead of 100ms\n", (long)res); + pr_warn("APIC calibration not consistent with PM-Timer: %ldms instead of 10= 0ms\n", + (long)res); =20 /* Correct the lapic counter value */ res =3D (((u64)(*delta)) * pm_100ms); @@ -707,9 +707,8 @@ calibrate_by_pmtimer(u32 deltapm, long *delta, long *delt= atsc) if (boot_cpu_has(X86_FEATURE_TSC)) { res =3D (((u64)(*deltatsc)) * pm_100ms); do_div(res, deltapm); - apic_printk(APIC_VERBOSE, "TSC delta adjusted to " - "PM-Timer: %lu (%ld)\n", - (unsigned long)res, *deltatsc); + apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n", + (unsigned long)res, *deltatsc); *deltatsc =3D (long)res; } =20 @@ -792,8 +791,7 @@ static int __init calibrate_APIC_clock(void) * in the clockevent structure and return. */ if (!lapic_init_clockevent()) { - apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", - lapic_timer_period); + apic_pr_verbose("lapic timer already calibrated %d\n", lapic_timer_period); /* * Direct calibration methods must have an always running * local APIC timer, no need for broadcast timer. @@ -802,8 +800,7 @@ static int __init calibrate_APIC_clock(void) return 0; } =20 - apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" - "calibrating APIC timer ...\n"); + apic_pr_verbose("Using local APIC timer interrupts. Calibrating APIC timer = ...\n"); =20 /* * There are platforms w/o global clockevent devices. Instead of @@ -866,7 +863,7 @@ static int __init calibrate_APIC_clock(void) =20 /* Build delta t1-t2 as apic timer counts down */ delta =3D lapic_cal_t1 - lapic_cal_t2; - apic_printk(APIC_VERBOSE, "... lapic delta =3D %ld\n", delta); + apic_pr_verbose("... lapic delta =3D %ld\n", delta); =20 deltatsc =3D (long)(lapic_cal_tsc2 - lapic_cal_tsc1); =20 @@ -877,22 +874,19 @@ static int __init calibrate_APIC_clock(void) lapic_timer_period =3D (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; lapic_init_clockevent(); =20 - apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); - apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); - apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", - lapic_timer_period); + apic_pr_verbose("..... delta %ld\n", delta); + apic_pr_verbose("..... mult: %u\n", lapic_clockevent.mult); + apic_pr_verbose("..... calibration result: %u\n", lapic_timer_period); =20 if (boot_cpu_has(X86_FEATURE_TSC)) { - apic_printk(APIC_VERBOSE, "..... CPU clock speed is " - "%ld.%04ld MHz.\n", - (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), - (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); + apic_pr_verbose("..... CPU clock speed is %ld.%04ld MHz.\n", + (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), + (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); } =20 - apic_printk(APIC_VERBOSE, "..... host bus clock speed is " - "%u.%04u MHz.\n", - lapic_timer_period / (1000000 / HZ), - lapic_timer_period % (1000000 / HZ)); + apic_pr_verbose("..... host bus clock speed is %u.%04u MHz.\n", + lapic_timer_period / (1000000 / HZ), + lapic_timer_period % (1000000 / HZ)); =20 /* * Do a sanity check on the APIC calibration result @@ -911,7 +905,7 @@ static int __init calibrate_APIC_clock(void) * available. */ if (!pm_referenced && global_clock_event) { - apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); + apic_pr_verbose("... verify APIC timer\n"); =20 /* * Setup the apic timer manually @@ -932,11 +926,11 @@ static int __init calibrate_APIC_clock(void) =20 /* Jiffies delta */ deltaj =3D lapic_cal_j2 - lapic_cal_j1; - apic_printk(APIC_VERBOSE, "... jiffies delta =3D %lu\n", deltaj); + apic_pr_verbose("... jiffies delta =3D %lu\n", deltaj); =20 /* Check, if the jiffies result is consistent */ if (deltaj >=3D LAPIC_CAL_LOOPS-2 && deltaj <=3D LAPIC_CAL_LOOPS+2) - apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); + apic_pr_verbose("... jiffies result ok\n"); else levt->features |=3D CLOCK_EVT_FEAT_DUMMY; } @@ -1221,9 +1215,8 @@ void __init sync_Arb_IDs(void) */ apic_wait_icr_idle(); =20 - apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); - apic_write(APIC_ICR, APIC_DEST_ALLINC | - APIC_INT_LEVELTRIG | APIC_DM_INIT); + apic_pr_debug("Synchronizing Arb IDs.\n"); + apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT); } =20 enum apic_intr_mode_id apic_intr_mode __ro_after_init; @@ -1409,10 +1402,10 @@ static void lapic_setup_esr(void) if (maxlvt > 3) apic_write(APIC_ESR, 0); value =3D apic_read(APIC_ESR); - if (value !=3D oldvalue) - apic_printk(APIC_VERBOSE, "ESR value before enabling " - "vector: 0x%08x after: 0x%08x\n", - oldvalue, value); + if (value !=3D oldvalue) { + apic_pr_verbose("ESR value before enabling vector: 0x%08x after: 0x%08x\n= ", + oldvalue, value); + } } =20 #define APIC_IR_REGS APIC_ISR_NR @@ -1599,10 +1592,10 @@ static void setup_local_APIC(void) value =3D apic_read(APIC_LVT0) & APIC_LVT_MASKED; if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { value =3D APIC_DM_EXTINT; - apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); + apic_pr_verbose("Enabled ExtINT on CPU#%d\n", cpu); } else { value =3D APIC_DM_EXTINT | APIC_LVT_MASKED; - apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); + apic_pr_verbose("Masked ExtINT on CPU#%d\n", cpu); } apic_write(APIC_LVT0, value); =20 @@ -2066,8 +2059,7 @@ static __init void apic_set_fixmap(bool read_apic) { set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); apic_mmio_base =3D APIC_BASE; - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", - apic_mmio_base, mp_lapic_addr); + apic_pr_verbose("Mapped APIC to %16lx (%16lx)\n", apic_mmio_base, mp_lapic_= addr); if (read_apic) apic_read_boot_cpu_id(false); } @@ -2170,18 +2162,17 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) apic_eoi(); atomic_inc(&irq_err_count); =20 - apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", - smp_processor_id(), v); + apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v); =20 v &=3D 0xff; while (v) { if (v & 0x1) - apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); + apic_pr_debug_cont(" : %s", error_interrupt_reason[i]); i++; v >>=3D 1; } =20 - apic_printk(APIC_DEBUG, KERN_CONT "\n"); + apic_pr_debug_cont("\n"); =20 trace_error_apic_exit(ERROR_APIC_VECTOR); } @@ -2201,8 +2192,7 @@ static void __init connect_bsp_APIC(void) * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's * local APIC to INT and NMI lines. */ - apic_printk(APIC_VERBOSE, "leaving PIC mode, " - "enabling APIC mode.\n"); + apic_pr_verbose("Leaving PIC mode, enabling APIC mode.\n"); imcr_pic_to_apic(); } #endif @@ -2227,8 +2217,7 @@ void disconnect_bsp_APIC(int virt_wire_setup) * IPIs, won't work beyond this point! The only exception are * INIT IPIs. */ - apic_printk(APIC_VERBOSE, "disabling APIC mode, " - "entering PIC mode.\n"); + apic_pr_verbose("Disabling APIC mode, entering PIC mode.\n"); imcr_apic_to_pic(); return; } diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_= flat_64.c index f37ad3392fec..e0308d8c4e6c 100644 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -8,129 +8,25 @@ * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and * James Cleverdon. */ -#include #include -#include =20 -#include #include =20 #include "local.h" =20 -static struct apic apic_physflat; -static struct apic apic_flat; - -struct apic *apic __ro_after_init =3D &apic_flat; -EXPORT_SYMBOL_GPL(apic); - -static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) -{ - return 1; -} - -static void _flat_send_IPI_mask(unsigned long mask, int vector) -{ - unsigned long flags; - - local_irq_save(flags); - __default_send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL); - local_irq_restore(flags); -} - -static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector) -{ - unsigned long mask =3D cpumask_bits(cpumask)[0]; - - _flat_send_IPI_mask(mask, vector); -} - -static void -flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) -{ - unsigned long mask =3D cpumask_bits(cpumask)[0]; - int cpu =3D smp_processor_id(); - - if (cpu < BITS_PER_LONG) - __clear_bit(cpu, &mask); - - _flat_send_IPI_mask(mask, vector); -} - -static u32 flat_get_apic_id(u32 x) +static u32 physflat_get_apic_id(u32 x) { return (x >> 24) & 0xFF; } =20 -static int flat_probe(void) +static int physflat_probe(void) { return 1; } =20 -static struct apic apic_flat __ro_after_init =3D { - .name =3D "flat", - .probe =3D flat_probe, - .acpi_madt_oem_check =3D flat_acpi_madt_oem_check, - - .dest_mode_logical =3D true, - - .disable_esr =3D 0, - - .init_apic_ldr =3D default_init_apic_ldr, - .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - - .max_apic_id =3D 0xFE, - .get_apic_id =3D flat_get_apic_id, - - .calc_dest_apicid =3D apic_flat_calc_apicid, - - .send_IPI =3D default_send_IPI_single, - .send_IPI_mask =3D flat_send_IPI_mask, - .send_IPI_mask_allbutself =3D flat_send_IPI_mask_allbutself, - .send_IPI_allbutself =3D default_send_IPI_allbutself, - .send_IPI_all =3D default_send_IPI_all, - .send_IPI_self =3D default_send_IPI_self, - .nmi_to_offline_cpu =3D true, - - .read =3D native_apic_mem_read, - .write =3D native_apic_mem_write, - .eoi =3D native_apic_mem_eoi, - .icr_read =3D native_apic_icr_read, - .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, -}; - -/* - * Physflat mode is used when there are more than 8 CPUs on a system. - * We cannot use logical delivery in this case because the mask - * overflows, so use physical mode. - */ static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) { -#ifdef CONFIG_ACPI - /* - * Quirk: some x86_64 machines can only use physical APIC mode - * regardless of how many processors are present (x86_64 ES7000 - * is an example). - */ - if (acpi_gbl_FADT.header.revision >=3D FADT2_REVISION_ID && - (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) { - printk(KERN_DEBUG "system APIC only can use physical flat"); - return 1; - } - - if (!strncmp(oem_id, "IBM", 3) && !strncmp(oem_table_id, "EXA", 3)) { - printk(KERN_DEBUG "IBM Summit detected, will use apic physical"); - return 1; - } -#endif - - return 0; -} - -static int physflat_probe(void) -{ - return apic =3D=3D &apic_physflat || num_possible_cpus() > 8 || jailhouse_p= aravirt(); + return 1; } =20 static struct apic apic_physflat __ro_after_init =3D { @@ -146,7 +42,7 @@ static struct apic apic_physflat __ro_after_init =3D { .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, - .get_apic_id =3D flat_get_apic_id, + .get_apic_id =3D physflat_get_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 @@ -166,8 +62,7 @@ static struct apic apic_physflat __ro_after_init =3D { .wait_icr_idle =3D apic_mem_wait_icr_idle, .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, }; +apic_driver(apic_physflat); =20 -/* - * We need to check for physflat first, so this order is important. - */ -apic_drivers(apic_physflat, apic_flat); +struct apic *apic __ro_after_init =3D &apic_physflat; +EXPORT_SYMBOL_GPL(apic); diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 477b740b2f26..1029ea4ac8ba 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -86,8 +86,8 @@ static unsigned int ioapic_dynirq_base; static int ioapic_initialized; =20 struct irq_pin_list { - struct list_head list; - int apic, pin; + struct list_head list; + int apic, pin; }; =20 struct mp_chip_data { @@ -96,7 +96,7 @@ struct mp_chip_data { bool is_level; bool active_low; bool isa_irq; - u32 count; + u32 count; }; =20 struct mp_ioapic_gsi { @@ -105,21 +105,17 @@ struct mp_ioapic_gsi { }; =20 static struct ioapic { - /* - * # of IRQ routing registers - */ - int nr_registers; - /* - * Saved state during suspend/resume, or while enabling intr-remap. - */ - struct IO_APIC_route_entry *saved_registers; + /* # of IRQ routing registers */ + int nr_registers; + /* Saved state during suspend/resume, or while enabling intr-remap. */ + struct IO_APIC_route_entry *saved_registers; /* I/O APIC config */ - struct mpc_ioapic mp_config; + struct mpc_ioapic mp_config; /* IO APIC gsi routing info */ - struct mp_ioapic_gsi gsi_config; - struct ioapic_domain_cfg irqdomain_cfg; - struct irq_domain *irqdomain; - struct resource *iomem_res; + struct mp_ioapic_gsi gsi_config; + struct ioapic_domain_cfg irqdomain_cfg; + struct irq_domain *irqdomain; + struct resource *iomem_res; } ioapics[MAX_IO_APICS]; =20 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver @@ -205,10 +201,9 @@ void mp_save_irq(struct mpc_intsrc *m) { int i; =20 - apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," - " IRQ %02x, APIC ID %x, APIC INT %02x\n", - m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, - m->srcbusirq, m->dstapic, m->dstirq); + apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID= %x, APIC INT %02x\n", + m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, + m->srcbusirq, m->dstapic, m->dstirq); =20 for (i =3D 0; i < mp_irq_entries; i++) { if (!memcmp(&mp_irqs[i], m, sizeof(*m))) @@ -269,12 +264,14 @@ static __attribute_const__ struct io_apic __iomem *io_a= pic_base(int idx) static inline void io_apic_eoi(unsigned int apic, unsigned int vector) { struct io_apic __iomem *io_apic =3D io_apic_base(apic); + writel(vector, &io_apic->eoi); } =20 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) { struct io_apic __iomem *io_apic =3D io_apic_base(apic); + writel(reg, &io_apic->index); return readl(&io_apic->data); } @@ -300,14 +297,8 @@ static struct IO_APIC_route_entry __ioapic_read_entry(in= t apic, int pin) =20 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) { - struct IO_APIC_route_entry entry; - unsigned long flags; - - raw_spin_lock_irqsave(&ioapic_lock, flags); - entry =3D __ioapic_read_entry(apic, pin); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - - return entry; + guard(raw_spinlock_irqsave)(&ioapic_lock); + return __ioapic_read_entry(apic, pin); } =20 /* @@ -324,11 +315,8 @@ static void __ioapic_write_entry(int apic, int pin, stru= ct IO_APIC_route_entry e =20 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry= e) { - unsigned long flags; - - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); __ioapic_write_entry(apic, pin, e); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -339,12 +327,10 @@ static void ioapic_write_entry(int apic, int pin, struc= t IO_APIC_route_entry e) static void ioapic_mask_entry(int apic, int pin) { struct IO_APIC_route_entry e =3D { .masked =3D true }; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); io_apic_write(apic, 0x10 + 2*pin, e.w1); io_apic_write(apic, 0x11 + 2*pin, e.w2); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -352,68 +338,39 @@ static void ioapic_mask_entry(int apic, int pin) * shared ISA-space IRQs, so we have to support them. We are super * fast in the common case, and fast for shared ISA-space IRQs. */ -static int __add_pin_to_irq_node(struct mp_chip_data *data, - int node, int apic, int pin) +static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int api= c, int pin) { struct irq_pin_list *entry; =20 - /* don't allow duplicates */ - for_each_irq_pin(entry, data->irq_2_pin) + /* Don't allow duplicates */ + for_each_irq_pin(entry, data->irq_2_pin) { if (entry->apic =3D=3D apic && entry->pin =3D=3D pin) - return 0; + return true; + } =20 entry =3D kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node); if (!entry) { - pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", - node, apic, pin); - return -ENOMEM; + pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin); + return false; } + entry->apic =3D apic; entry->pin =3D pin; list_add_tail(&entry->list, &data->irq_2_pin); - - return 0; + return true; } =20 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int p= in) { struct irq_pin_list *tmp, *entry; =20 - list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) + list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) { if (entry->apic =3D=3D apic && entry->pin =3D=3D pin) { list_del(&entry->list); kfree(entry); return; } -} - -static void add_pin_to_irq_node(struct mp_chip_data *data, - int node, int apic, int pin) -{ - if (__add_pin_to_irq_node(data, node, apic, pin)) - panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); -} - -/* - * Reroute an IRQ to a different pin. - */ -static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int no= de, - int oldapic, int oldpin, - int newapic, int newpin) -{ - struct irq_pin_list *entry; - - for_each_irq_pin(entry, data->irq_2_pin) { - if (entry->apic =3D=3D oldapic && entry->pin =3D=3D oldpin) { - entry->apic =3D newapic; - entry->pin =3D newpin; - /* every one is different, right? */ - return; - } } - - /* old apic/pin didn't exist, so just add new ones */ - add_pin_to_irq_node(data, node, newapic, newpin); } =20 static void io_apic_modify_irq(struct mp_chip_data *data, bool masked, @@ -430,12 +387,12 @@ static void io_apic_modify_irq(struct mp_chip_data *dat= a, bool masked, } } =20 +/* + * Synchronize the IO-APIC and the CPU by doing a dummy read from the + * IO-APIC + */ static void io_apic_sync(struct irq_pin_list *entry) { - /* - * Synchronize the IO-APIC and the CPU by doing - * a dummy read from the IO-APIC - */ struct io_apic __iomem *io_apic; =20 io_apic =3D io_apic_base(entry->apic); @@ -445,11 +402,9 @@ static void io_apic_sync(struct irq_pin_list *entry) static void mask_ioapic_irq(struct irq_data *irq_data) { struct mp_chip_data *data =3D irq_data->chip_data; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); io_apic_modify_irq(data, true, &io_apic_sync); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void __unmask_ioapic(struct mp_chip_data *data) @@ -460,11 +415,9 @@ static void __unmask_ioapic(struct mp_chip_data *data) static void unmask_ioapic_irq(struct irq_data *irq_data) { struct mp_chip_data *data =3D irq_data->chip_data; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); __unmask_ioapic(data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -492,30 +445,24 @@ static void __eoi_ioapic_pin(int apic, int pin, int vec= tor) =20 entry =3D entry1 =3D __ioapic_read_entry(apic, pin); =20 - /* - * Mask the entry and change the trigger mode to edge. - */ + /* Mask the entry and change the trigger mode to edge. */ entry1.masked =3D true; entry1.is_level =3D false; =20 __ioapic_write_entry(apic, pin, entry1); =20 - /* - * Restore the previous level triggered entry. - */ + /* Restore the previous level triggered entry. */ __ioapic_write_entry(apic, pin, entry); } } =20 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data) { - unsigned long flags; struct irq_pin_list *entry; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); for_each_irq_pin(entry, data->irq_2_pin) __eoi_ioapic_pin(entry->apic, entry->pin, vector); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) @@ -538,8 +485,6 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned= int pin) } =20 if (entry.irr) { - unsigned long flags; - /* * Make sure the trigger mode is set to level. Explicit EOI * doesn't clear the remote-IRR if the trigger mode is not @@ -549,9 +494,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned= int pin) entry.is_level =3D true; ioapic_write_entry(apic, pin, entry); } - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); __eoi_ioapic_pin(apic, pin, entry.vector); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 /* @@ -586,28 +530,23 @@ static int pirq_entries[MAX_PIRQS] =3D { =20 static int __init ioapic_pirq_setup(char *str) { - int i, max; - int ints[MAX_PIRQS+1]; + int i, max, ints[MAX_PIRQS+1]; =20 get_options(str, ARRAY_SIZE(ints), ints); =20 - apic_printk(APIC_VERBOSE, KERN_INFO - "PIRQ redirection, working around broken MP-BIOS.\n"); + apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n"); + max =3D MAX_PIRQS; if (ints[0] < MAX_PIRQS) max =3D ints[0]; =20 for (i =3D 0; i < max; i++) { - apic_printk(APIC_VERBOSE, KERN_DEBUG - "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); - /* - * PIRQs are mapped upside down, usually. - */ + apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]); + /* PIRQs are mapped upside down, usually */ pirq_entries[MAX_PIRQS-i-1] =3D ints[i+1]; } return 1; } - __setup("pirq=3D", ioapic_pirq_setup); #endif /* CONFIG_X86_32 */ =20 @@ -626,8 +565,7 @@ int save_ioapic_entries(void) } =20 for_each_pin(apic, pin) - ioapics[apic].saved_registers[pin] =3D - ioapic_read_entry(apic, pin); + ioapics[apic].saved_registers[pin] =3D ioapic_read_entry(apic, pin); } =20 return err; @@ -668,8 +606,7 @@ int restore_ioapic_entries(void) continue; =20 for_each_pin(apic, pin) - ioapic_write_entry(apic, pin, - ioapics[apic].saved_registers[pin]); + ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]); } return 0; } @@ -681,12 +618,13 @@ static int find_irq_entry(int ioapic_idx, int pin, int = type) { int i; =20 - for (i =3D 0; i < mp_irq_entries; i++) + for (i =3D 0; i < mp_irq_entries; i++) { if (mp_irqs[i].irqtype =3D=3D type && (mp_irqs[i].dstapic =3D=3D mpc_ioapic_id(ioapic_idx) || mp_irqs[i].dstapic =3D=3D MP_APIC_ALL) && mp_irqs[i].dstirq =3D=3D pin) return i; + } =20 return -1; } @@ -701,10 +639,8 @@ static int __init find_isa_irq_pin(int irq, int type) for (i =3D 0; i < mp_irq_entries; i++) { int lbus =3D mp_irqs[i].srcbus; =20 - if (test_bit(lbus, mp_bus_not_pci) && - (mp_irqs[i].irqtype =3D=3D type) && + if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype =3D=3D type) && (mp_irqs[i].srcbusirq =3D=3D irq)) - return mp_irqs[i].dstirq; } return -1; @@ -717,8 +653,7 @@ static int __init find_isa_irq_apic(int irq, int type) for (i =3D 0; i < mp_irq_entries; i++) { int lbus =3D mp_irqs[i].srcbus; =20 - if (test_bit(lbus, mp_bus_not_pci) && - (mp_irqs[i].irqtype =3D=3D type) && + if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype =3D=3D type) && (mp_irqs[i].srcbusirq =3D=3D irq)) break; } @@ -726,9 +661,10 @@ static int __init find_isa_irq_apic(int irq, int type) if (i < mp_irq_entries) { int ioapic_idx; =20 - for_each_ioapic(ioapic_idx) + for_each_ioapic(ioapic_idx) { if (mpc_ioapic_id(ioapic_idx) =3D=3D mp_irqs[i].dstapic) return ioapic_idx; + } } =20 return -1; @@ -769,8 +705,7 @@ static bool EISA_ELCR(unsigned int irq) unsigned int port =3D PIC_ELCR1 + (irq >> 3); return (inb(port) >> (irq & 7)) & 1; } - apic_printk(APIC_VERBOSE, KERN_INFO - "Broken MPtable reports ISA irq %d\n", irq); + apic_pr_verbose("Broken MPtable reports ISA irq %d\n", irq); return false; } =20 @@ -947,9 +882,9 @@ static bool mp_check_pin_attr(int irq, struct irq_alloc_i= nfo *info) static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 = gsi, struct irq_alloc_info *info) { + int type =3D ioapics[ioapic].irqdomain_cfg.type; bool legacy =3D false; int irq =3D -1; - int type =3D ioapics[ioapic].irqdomain_cfg.type; =20 switch (type) { case IOAPIC_DOMAIN_LEGACY: @@ -971,8 +906,7 @@ static int alloc_irq_from_domain(struct irq_domain *domai= n, int ioapic, u32 gsi, return -1; } =20 - return __irq_domain_alloc_irqs(domain, irq, 1, - ioapic_alloc_attr_node(info), + return __irq_domain_alloc_irqs(domain, irq, 1, ioapic_alloc_attr_node(info), info, legacy, NULL); } =20 @@ -986,13 +920,12 @@ static int alloc_irq_from_domain(struct irq_domain *dom= ain, int ioapic, u32 gsi, * PIRQs instead of reprogramming the interrupt routing logic. Thus there ma= y be * multiple pins sharing the same legacy IRQ number when ACPI is disabled. */ -static int alloc_isa_irq_from_domain(struct irq_domain *domain, - int irq, int ioapic, int pin, +static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int= ioapic, int pin, struct irq_alloc_info *info) { - struct mp_chip_data *data; struct irq_data *irq_data =3D irq_get_irq_data(irq); int node =3D ioapic_alloc_attr_node(info); + struct mp_chip_data *data; =20 /* * Legacy ISA IRQ has already been allocated, just add pin to @@ -1002,13 +935,11 @@ static int alloc_isa_irq_from_domain(struct irq_domain= *domain, if (irq_data && irq_data->parent_data) { if (!mp_check_pin_attr(irq, info)) return -EBUSY; - if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, - info->ioapic.pin)) + if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic.p= in)) return -ENOMEM; } else { info->flags |=3D X86_IRQ_ALLOC_LEGACY; - irq =3D __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, - NULL); + irq =3D __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, NULL); if (irq >=3D 0) { irq_data =3D irq_domain_get_irq_data(domain, irq); data =3D irq_data->chip_data; @@ -1022,11 +953,11 @@ static int alloc_isa_irq_from_domain(struct irq_domain= *domain, static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, unsigned int flags, struct irq_alloc_info *info) { - int irq; - bool legacy =3D false; + struct irq_domain *domain =3D mp_ioapic_irqdomain(ioapic); struct irq_alloc_info tmp; struct mp_chip_data *data; - struct irq_domain *domain =3D mp_ioapic_irqdomain(ioapic); + bool legacy =3D false; + int irq; =20 if (!domain) return -ENOSYS; @@ -1046,7 +977,7 @@ static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapi= c, int pin, return -EINVAL; } =20 - mutex_lock(&ioapic_mutex); + guard(mutex)(&ioapic_mutex); if (!(flags & IOAPIC_MAP_ALLOC)) { if (!legacy) { irq =3D irq_find_mapping(domain, pin); @@ -1067,8 +998,6 @@ static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapi= c, int pin, data->count++; } } - mutex_unlock(&ioapic_mutex); - return irq; } =20 @@ -1076,26 +1005,20 @@ static int pin_2_irq(int idx, int ioapic, int pin, un= signed int flags) { u32 gsi =3D mp_pin_to_gsi(ioapic, pin); =20 - /* - * Debugging check, we are in big trouble if this message pops up! - */ + /* Debugging check, we are in big trouble if this message pops up! */ if (mp_irqs[idx].dstirq !=3D pin) pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); =20 #ifdef CONFIG_X86_32 - /* - * PCI IRQ command line redirection. Yes, limits are hardcoded. - */ + /* PCI IRQ command line redirection. Yes, limits are hardcoded. */ if ((pin >=3D 16) && (pin <=3D 23)) { - if (pirq_entries[pin-16] !=3D -1) { - if (!pirq_entries[pin-16]) { - apic_printk(APIC_VERBOSE, KERN_DEBUG - "disabling PIRQ%d\n", pin-16); + if (pirq_entries[pin - 16] !=3D -1) { + if (!pirq_entries[pin - 16]) { + apic_pr_verbose("Disabling PIRQ%d\n", pin - 16); } else { int irq =3D pirq_entries[pin-16]; - apic_printk(APIC_VERBOSE, KERN_DEBUG - "using PIRQ%d -> IRQ %d\n", - pin-16, irq); + + apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq); return irq; } } @@ -1133,10 +1056,9 @@ void mp_unmap_irq(int irq) if (!data || data->isa_irq) return; =20 - mutex_lock(&ioapic_mutex); + guard(mutex)(&ioapic_mutex); if (--data->count =3D=3D 0) irq_domain_free_irqs(irq, 1); - mutex_unlock(&ioapic_mutex); } =20 /* @@ -1147,12 +1069,10 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int= pin) { int irq, i, best_ioapic =3D -1, best_idx =3D -1; =20 - apic_printk(APIC_DEBUG, - "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", - bus, slot, pin); + apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", + bus, slot, pin); if (test_bit(bus, mp_bus_not_pci)) { - apic_printk(APIC_VERBOSE, - "PCI BIOS passed nonexistent PCI bus %d!\n", bus); + apic_pr_verbose("PCI BIOS passed nonexistent PCI bus %d!\n", bus); return -1; } =20 @@ -1197,8 +1117,7 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int p= in) return -1; =20 out: - return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, - IOAPIC_MAP_ALLOC); + return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, IOAPIC_MA= P_ALLOC); } EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); =20 @@ -1209,17 +1128,16 @@ static void __init setup_IO_APIC_irqs(void) unsigned int ioapic, pin; int idx; =20 - apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); + apic_pr_verbose("Init IO_APIC IRQs\n"); =20 for_each_ioapic_pin(ioapic, pin) { idx =3D find_irq_entry(ioapic, pin, mp_INT); - if (idx < 0) - apic_printk(APIC_VERBOSE, - KERN_DEBUG " apic %d pin %d not connected\n", - mpc_ioapic_id(ioapic), pin); - else - pin_2_irq(idx, ioapic, pin, - ioapic ? 0 : IOAPIC_MAP_ALLOC); + if (idx < 0) { + apic_pr_verbose("apic %d pin %d not connected\n", + mpc_ioapic_id(ioapic), pin); + } else { + pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC); + } } } =20 @@ -1234,26 +1152,21 @@ static void io_apic_print_entries(unsigned int apic, = unsigned int nr_entries) char buf[256]; int i; =20 - printk(KERN_DEBUG "IOAPIC %d:\n", apic); + apic_dbg("IOAPIC %d:\n", apic); for (i =3D 0; i <=3D nr_entries; i++) { entry =3D ioapic_read_entry(apic, i); - snprintf(buf, sizeof(buf), - " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", - i, - entry.masked ? "disabled" : "enabled ", + snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d= )", + i, entry.masked ? "disabled" : "enabled ", entry.is_level ? "level" : "edge ", entry.active_low ? "low " : "high", entry.vector, entry.irr, entry.delivery_status); if (entry.ir_format) { - printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", - buf, - (entry.ir_index_15 << 15) | entry.ir_index_0_14, - entry.ir_zero); + apic_dbg("%s, remapped, I(%04X), Z(%X)\n", buf, + (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero); } else { - printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf, - entry.dest_mode_logical ? "logical " : "physical", - entry.virt_destid_8_14, entry.destid_0_7, - entry.delivery_mode); + apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf, + entry.dest_mode_logical ? "logical " : "physic al", + entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode); } } } @@ -1264,30 +1177,25 @@ static void __init print_IO_APIC(int ioapic_idx) union IO_APIC_reg_01 reg_01; union IO_APIC_reg_02 reg_02; union IO_APIC_reg_03 reg_03; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic_idx, 0); - reg_01.raw =3D io_apic_read(ioapic_idx, 1); - if (reg_01.bits.version >=3D 0x10) - reg_02.raw =3D io_apic_read(ioapic_idx, 2); - if (reg_01.bits.version >=3D 0x20) - reg_03.raw =3D io_apic_read(ioapic_idx, 3); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - - printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); - printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); - printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); - printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_= type); - printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); - - printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); - printk(KERN_DEBUG "....... : max redirection entries: %02X\n", - reg_01.bits.entries); - - printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); - printk(KERN_DEBUG "....... : IO APIC version: %02X\n", - reg_01.bits.version); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + reg_00.raw =3D io_apic_read(ioapic_idx, 0); + reg_01.raw =3D io_apic_read(ioapic_idx, 1); + if (reg_01.bits.version >=3D 0x10) + reg_02.raw =3D io_apic_read(ioapic_idx, 2); + if (reg_01.bits.version >=3D 0x20) + reg_03.raw =3D io_apic_read(ioapic_idx, 3); + } + + apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); + apic_dbg(".... register #00: %08X\n", reg_00.raw); + apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID); + apic_dbg("....... : Delivery Type: %X\n", reg_00.bits.delivery_type); + apic_dbg("....... : LTS : %X\n", reg_00.bits.LTS); + apic_dbg(".... register #01: %08X\n", *(int *)®_01); + apic_dbg("....... : max redirection entries: %02X\n", reg_01.bits.entri= es); + apic_dbg("....... : PRQ implemented: %X\n", reg_01.bits.PRQ); + apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version); =20 /* * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, @@ -1295,8 +1203,8 @@ static void __init print_IO_APIC(int ioapic_idx) * value, so ignore it if reg_02 =3D=3D reg_01. */ if (reg_01.bits.version >=3D 0x10 && reg_02.raw !=3D reg_01.raw) { - printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); - printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitra= tion); + apic_dbg(".... register #02: %08X\n", reg_02.raw); + apic_dbg("....... : arbitration: %02X\n", reg_02.bits.arbitration); } =20 /* @@ -1306,11 +1214,11 @@ static void __init print_IO_APIC(int ioapic_idx) */ if (reg_01.bits.version >=3D 0x20 && reg_03.raw !=3D reg_02.raw && reg_03.raw !=3D reg_01.raw) { - printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); - printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); + apic_dbg(".... register #03: %08X\n", reg_03.raw); + apic_dbg("....... : Boot DT : %X\n", reg_03.bits.boot_DT); } =20 - printk(KERN_DEBUG ".... IRQ redirection table:\n"); + apic_dbg(".... IRQ redirection table:\n"); io_apic_print_entries(ioapic_idx, reg_01.bits.entries); } =20 @@ -1319,11 +1227,11 @@ void __init print_IO_APICs(void) int ioapic_idx; unsigned int irq; =20 - printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); - for_each_ioapic(ioapic_idx) - printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", - mpc_ioapic_id(ioapic_idx), - ioapics[ioapic_idx].nr_registers); + apic_dbg("number of MP IRQ sources: %d.\n", mp_irq_entries); + for_each_ioapic(ioapic_idx) { + apic_dbg("number of IO-APIC #%d registers: %d.\n", + mpc_ioapic_id(ioapic_idx), ioapics[ioapic_idx].nr_registers); + } =20 /* * We are a bit conservative about what we expect. We have to @@ -1334,7 +1242,7 @@ void __init print_IO_APICs(void) for_each_ioapic(ioapic_idx) print_IO_APIC(ioapic_idx); =20 - printk(KERN_DEBUG "IRQ to pin mappings:\n"); + apic_dbg("IRQ to pin mappings:\n"); for_each_active_irq(irq) { struct irq_pin_list *entry; struct irq_chip *chip; @@ -1349,7 +1257,7 @@ void __init print_IO_APICs(void) if (list_empty(&data->irq_2_pin)) continue; =20 - printk(KERN_DEBUG "IRQ%d ", irq); + apic_dbg("IRQ%d ", irq); for_each_irq_pin(entry, data->irq_2_pin) pr_cont("-> %d:%d", entry->apic, entry->pin); pr_cont("\n"); @@ -1363,8 +1271,7 @@ static struct { int pin, apic; } ioapic_i8259 =3D { -1,= -1 }; =20 void __init enable_IO_APIC(void) { - int i8259_apic, i8259_pin; - int apic, pin; + int i8259_apic, i8259_pin, apic, pin; =20 if (ioapic_is_disabled) nr_ioapics =3D 0; @@ -1376,19 +1283,21 @@ void __init enable_IO_APIC(void) /* See if any of the pins is in ExtINT mode */ struct IO_APIC_route_entry entry =3D ioapic_read_entry(apic, pin); =20 - /* If the interrupt line is enabled and in ExtInt mode - * I have found the pin where the i8259 is connected. + /* + * If the interrupt line is enabled and in ExtInt mode I + * have found the pin where the i8259 is connected. */ - if (!entry.masked && - entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTINT) { + if (!entry.masked && entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTINT)= { ioapic_i8259.apic =3D apic; ioapic_i8259.pin =3D pin; - goto found_i8259; + break; } } - found_i8259: - /* Look to see what if the MP table has reported the ExtINT */ - /* If we could not find the appropriate pin by looking at the ioapic + + /* + * Look to see what if the MP table has reported the ExtINT + * + * If we could not find the appropriate pin by looking at the ioapic * the i8259 probably is not connected the ioapic but give the * mptable a chance anyway. */ @@ -1396,29 +1305,24 @@ void __init enable_IO_APIC(void) i8259_apic =3D find_isa_irq_apic(0, mp_ExtINT); /* Trust the MP table if nothing is setup in the hardware */ if ((ioapic_i8259.pin =3D=3D -1) && (i8259_pin >=3D 0)) { - printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table= \n"); + pr_warn("ExtINT not setup in hardware but reported by MP table\n"); ioapic_i8259.pin =3D i8259_pin; ioapic_i8259.apic =3D i8259_apic; } /* Complain if the MP table and the hardware disagree */ if (((ioapic_i8259.apic !=3D i8259_apic) || (ioapic_i8259.pin !=3D i8259_pi= n)) && - (i8259_pin >=3D 0) && (ioapic_i8259.pin >=3D 0)) - { - printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); - } + (i8259_pin >=3D 0) && (ioapic_i8259.pin >=3D 0)) + pr_warn("ExtINT in hardware and MP table differ\n"); =20 - /* - * Do not trust the IO-APIC being empty at bootup - */ + /* Do not trust the IO-APIC being empty at bootup */ clear_IO_APIC(); } =20 void native_restore_boot_irq_mode(void) { /* - * If the i8259 is routed through an IOAPIC - * Put that IOAPIC in virtual wire mode - * so legacy interrupts can be delivered. + * If the i8259 is routed through an IOAPIC Put that IOAPIC in + * virtual wire mode so legacy interrupts can be delivered. */ if (ioapic_i8259.pin !=3D -1) { struct IO_APIC_route_entry entry; @@ -1433,9 +1337,7 @@ void native_restore_boot_irq_mode(void) entry.destid_0_7 =3D apic_id & 0xFF; entry.virt_destid_8_14 =3D apic_id >> 8; =20 - /* - * Add it to the IO-APIC irq-routing table: - */ + /* Add it to the IO-APIC irq-routing table */ ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); } =20 @@ -1464,7 +1366,6 @@ static void __init setup_ioapic_ids_from_mpc_nocheck(vo= id) const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned char old_id; - unsigned long flags; int ioapic_idx, i; =20 /* @@ -1478,9 +1379,8 @@ static void __init setup_ioapic_ids_from_mpc_nocheck(vo= id) */ for_each_ioapic(ioapic_idx) { /* Read the register 0 value */ - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic_idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) + reg_00.raw =3D io_apic_read(ioapic_idx, 0); =20 old_id =3D mpc_ioapic_id(ioapic_idx); =20 @@ -1508,47 +1408,42 @@ static void __init setup_ioapic_ids_from_mpc_nocheck(= void) set_bit(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { - apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", - mpc_ioapic_id(ioapic_idx)); + apic_pr_verbose("Setting %d in the phys_id_present_map\n", + mpc_ioapic_id(ioapic_idx)); set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map); } =20 /* - * We need to adjust the IRQ routing table - * if the ID changed. + * We need to adjust the IRQ routing table if the ID + * changed. */ - if (old_id !=3D mpc_ioapic_id(ioapic_idx)) - for (i =3D 0; i < mp_irq_entries; i++) + if (old_id !=3D mpc_ioapic_id(ioapic_idx)) { + for (i =3D 0; i < mp_irq_entries; i++) { if (mp_irqs[i].dstapic =3D=3D old_id) - mp_irqs[i].dstapic - =3D mpc_ioapic_id(ioapic_idx); + mp_irqs[i].dstapic =3D mpc_ioapic_id(ioapic_idx); + } + } =20 /* - * Update the ID register according to the right value - * from the MPC table if they are different. + * Update the ID register according to the right value from + * the MPC table if they are different. */ if (mpc_ioapic_id(ioapic_idx) =3D=3D reg_00.bits.ID) continue; =20 - apic_printk(APIC_VERBOSE, KERN_INFO - "...changing IO-APIC physical APIC ID to %d ...", - mpc_ioapic_id(ioapic_idx)); + apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...", + mpc_ioapic_id(ioapic_idx)); =20 reg_00.bits.ID =3D mpc_ioapic_id(ioapic_idx); - raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(ioapic_idx, 0, reg_00.raw); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - - /* - * Sanity check - */ - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic_idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + io_apic_write(ioapic_idx, 0, reg_00.raw); + reg_00.raw =3D io_apic_read(ioapic_idx, 0); + } + /* Sanity check */ if (reg_00.bits.ID !=3D mpc_ioapic_id(ioapic_idx)) pr_cont("could not set ID!\n"); else - apic_printk(APIC_VERBOSE, " ok.\n"); + apic_pr_verbose(" ok.\n"); } } =20 @@ -1593,8 +1488,7 @@ static void __init delay_with_tsc(void) do { rep_nop(); now =3D rdtsc(); - } while ((now - start) < 40000000000ULL / HZ && - time_before_eq(jiffies, end)); + } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, end= )); } =20 static void __init delay_without_tsc(void) @@ -1655,36 +1549,29 @@ static int __init timer_irq_works(void) * so we 'resend' these IRQs via IPIs, to the same CPU. It's much * better to do it this way as thus we do not have to be aware of * 'pending' interrupts in the IRQ path, except at this point. - */ -/* - * Edge triggered needs to resend any interrupt - * that was delayed but this is now handled in the device - * independent code. - */ - -/* - * Starting up a edge-triggered IO-APIC interrupt is - * nasty - we need to make sure that we get the edge. - * If it is already asserted for some reason, we need - * return 1 to indicate that is was pending. * - * This is not complete - we should be able to fake - * an edge even if it isn't on the 8259A... + * + * Edge triggered needs to resend any interrupt that was delayed but this + * is now handled in the device independent code. + * + * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to + * make sure that we get the edge. If it is already asserted for some + * reason, we need return 1 to indicate that is was pending. + * + * This is not complete - we should be able to fake an edge even if it + * isn't on the 8259A... */ static unsigned int startup_ioapic_irq(struct irq_data *data) { int was_pending =3D 0, irq =3D data->irq; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); if (irq < nr_legacy_irqs()) { legacy_pic->mask(irq); if (legacy_pic->irq_pending(irq)) was_pending =3D 1; } __unmask_ioapic(data->chip_data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - return was_pending; } =20 @@ -1694,9 +1581,8 @@ atomic_t irq_mis_count; static bool io_apic_level_ack_pending(struct mp_chip_data *data) { struct irq_pin_list *entry; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); for_each_irq_pin(entry, data->irq_2_pin) { struct IO_APIC_route_entry e; int pin; @@ -1704,13 +1590,9 @@ static bool io_apic_level_ack_pending(struct mp_chip_d= ata *data) pin =3D entry->pin; e.w1 =3D io_apic_read(entry->apic, 0x10 + pin*2); /* Is the remote IRR bit set? */ - if (e.irr) { - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + if (e.irr) return true; - } } - raw_spin_unlock_irqrestore(&ioapic_lock, flags); - return false; } =20 @@ -1728,7 +1610,8 @@ static inline bool ioapic_prepare_move(struct irq_data = *data) static inline void ioapic_finish_move(struct irq_data *data, bool moveit) { if (unlikely(moveit)) { - /* Only migrate the irq if the ack has been received. + /* + * Only migrate the irq if the ack has been received. * * On rare occasions the broadcast level triggered ack gets * delayed going to ioapics, and if we reprogram the @@ -1911,18 +1794,16 @@ static void ioapic_configure_entry(struct irq_data *i= rqd) __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); } =20 -static int ioapic_set_affinity(struct irq_data *irq_data, - const struct cpumask *mask, bool force) +static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpuma= sk *mask, bool force) { struct irq_data *parent =3D irq_data->parent_data; - unsigned long flags; int ret; =20 ret =3D parent->chip->irq_set_affinity(parent, mask, force); - raw_spin_lock_irqsave(&ioapic_lock, flags); + + guard(raw_spinlock_irqsave)(&ioapic_lock); if (ret >=3D 0 && ret !=3D IRQ_SET_MASK_OK_DONE) ioapic_configure_entry(irq_data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 return ret; } @@ -1941,9 +1822,8 @@ static int ioapic_set_affinity(struct irq_data *irq_dat= a, * * Verify that the corresponding Remote-IRR bits are clear. */ -static int ioapic_irq_get_chip_state(struct irq_data *irqd, - enum irqchip_irq_state which, - bool *state) +static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_irq= _state which, + bool *state) { struct mp_chip_data *mcd =3D irqd->chip_data; struct IO_APIC_route_entry rentry; @@ -1953,7 +1833,8 @@ static int ioapic_irq_get_chip_state(struct irq_data *i= rqd, return -EINVAL; =20 *state =3D false; - raw_spin_lock(&ioapic_lock); + + guard(raw_spinlock)(&ioapic_lock); for_each_irq_pin(p, mcd->irq_2_pin) { rentry =3D __ioapic_read_entry(p->apic, p->pin); /* @@ -1967,7 +1848,6 @@ static int ioapic_irq_get_chip_state(struct irq_data *i= rqd, break; } } - raw_spin_unlock(&ioapic_lock); return 0; } =20 @@ -2008,14 +1888,13 @@ static inline void init_IO_APIC_traps(void) cfg =3D irq_cfg(irq); if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { /* - * Hmm.. We don't have an entry for this, - * so default to an old-fashioned 8259 - * interrupt if we can.. + * Hmm.. We don't have an entry for this, so + * default to an old-fashioned 8259 interrupt if we + * can. Otherwise set the dummy interrupt chip. */ if (irq < nr_legacy_irqs()) legacy_pic->make_irq(irq); else - /* Strange. Oh, well.. */ irq_set_chip(irq, &no_irq_chip); } } @@ -2024,20 +1903,17 @@ static inline void init_IO_APIC_traps(void) /* * The local APIC irq-chip implementation: */ - static void mask_lapic_irq(struct irq_data *data) { - unsigned long v; + unsigned long v =3D apic_read(APIC_LVT0); =20 - v =3D apic_read(APIC_LVT0); apic_write(APIC_LVT0, v | APIC_LVT_MASKED); } =20 static void unmask_lapic_irq(struct irq_data *data) { - unsigned long v; + unsigned long v =3D apic_read(APIC_LVT0); =20 - v =3D apic_read(APIC_LVT0); apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); } =20 @@ -2056,8 +1932,7 @@ static struct irq_chip lapic_chip __read_mostly =3D { static void lapic_register_intr(int irq) { irq_clear_status_flags(irq, IRQ_LEVEL); - irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, - "edge"); + irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge"); } =20 /* @@ -2069,9 +1944,9 @@ static void lapic_register_intr(int irq) */ static inline void __init unlock_ExtINT_logic(void) { - int apic, pin, i; - struct IO_APIC_route_entry entry0, entry1; unsigned char save_control, save_freq_select; + struct IO_APIC_route_entry entry0, entry1; + int apic, pin, i; u32 apic_id; =20 pin =3D find_isa_irq_pin(8, mp_INT); @@ -2131,10 +2006,10 @@ static int __init disable_timer_pin_setup(char *arg) } early_param("disable_timer_pin_1", disable_timer_pin_setup); =20 -static int mp_alloc_timer_irq(int ioapic, int pin) +static int __init mp_alloc_timer_irq(int ioapic, int pin) { - int irq =3D -1; struct irq_domain *domain =3D mp_ioapic_irqdomain(ioapic); + int irq =3D -1; =20 if (domain) { struct irq_alloc_info info; @@ -2142,21 +2017,36 @@ static int mp_alloc_timer_irq(int ioapic, int pin) ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); info.devid =3D mpc_ioapic_id(ioapic); info.ioapic.pin =3D pin; - mutex_lock(&ioapic_mutex); + guard(mutex)(&ioapic_mutex); irq =3D alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); - mutex_unlock(&ioapic_mutex); } =20 return irq; } =20 +static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int no= de, + int oldapic, int oldpin, + int newapic, int newpin) +{ + struct irq_pin_list *entry; + + for_each_irq_pin(entry, data->irq_2_pin) { + if (entry->apic =3D=3D oldapic && entry->pin =3D=3D oldpin) { + entry->apic =3D newapic; + entry->pin =3D newpin; + return; + } + } + + /* Old apic/pin didn't exist, so just add a new one */ + add_pin_to_irq_node(data, node, newapic, newpin); +} + /* * This code may look a bit paranoid, but it's supposed to cooperate with * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ * is so screwy. Thanks to Brian Perkins for testing/hacking this beast * fanatically on his truly buggy board. - * - * FIXME: really need to revamp this for all platforms. */ static inline void __init check_timer(void) { @@ -2194,9 +2084,8 @@ static inline void __init check_timer(void) pin2 =3D ioapic_i8259.pin; apic2 =3D ioapic_i8259.apic; =20 - apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=3D0x%02X " - "apic1=3D%d pin1=3D%d apic2=3D%d pin2=3D%d\n", - cfg->vector, apic1, pin1, apic2, pin2); + pr_info("..TIMER: vector=3D0x%02X apic1=3D%d pin1=3D%d apic2=3D%d pin2=3D%d= \n", + cfg->vector, apic1, pin1, apic2, pin2); =20 /* * Some BIOS writers are clueless and report the ExtINTA @@ -2240,13 +2129,10 @@ static inline void __init check_timer(void) panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"= ); clear_IO_APIC_pin(apic1, pin1); if (!no_pin1) - apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " - "8254 timer not connected to IO-APIC\n"); + pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); =20 - apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " - "(IRQ0) through the 8259A ...\n"); - apic_printk(APIC_QUIET, KERN_INFO - "..... (found apic %d pin %d) ...\n", apic2, pin2); + pr_info("...trying to set up timer (IRQ0) through the 8259A ...\n"); + pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2); /* * legacy devices should be connected to IO APIC #0 */ @@ -2255,7 +2141,7 @@ static inline void __init check_timer(void) irq_domain_activate_irq(irq_data, false); legacy_pic->unmask(0); if (timer_irq_works()) { - apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); + pr_info("....... works.\n"); goto out; } /* @@ -2263,26 +2149,24 @@ static inline void __init check_timer(void) */ legacy_pic->mask(0); clear_IO_APIC_pin(apic2, pin2); - apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); + pr_info("....... failed.\n"); } =20 - apic_printk(APIC_QUIET, KERN_INFO - "...trying to set up timer as Virtual Wire IRQ...\n"); + pr_info("...trying to set up timer as Virtual Wire IRQ...\n"); =20 lapic_register_intr(0); apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ legacy_pic->unmask(0); =20 if (timer_irq_works()) { - apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); + pr_info("..... works.\n"); goto out; } legacy_pic->mask(0); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); - apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); + pr_info("..... failed.\n"); =20 - apic_printk(APIC_QUIET, KERN_INFO - "...trying to set up timer as ExtINT IRQ...\n"); + pr_info("...trying to set up timer as ExtINT IRQ...\n"); =20 legacy_pic->init(0); legacy_pic->make_irq(0); @@ -2292,14 +2176,15 @@ static inline void __init check_timer(void) unlock_ExtINT_logic(); =20 if (timer_irq_works()) { - apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); + pr_info("..... works.\n"); goto out; } - apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); - if (apic_is_x2apic_enabled()) - apic_printk(APIC_QUIET, KERN_INFO - "Perhaps problem with the pre-enabled x2apic mode\n" - "Try booting with x2apic and interrupt-remapping disabled in the bios= .\n"); + + pr_info("..... failed :\n"); + if (apic_is_x2apic_enabled()) { + pr_info("Perhaps problem with the pre-enabled x2apic mode\n" + "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"= ); + } panic("IO-APIC + timer doesn't work! Boot with apic=3Ddebug and send a " "report. Then try booting with the 'noapic' option.\n"); out: @@ -2327,11 +2212,11 @@ static inline void __init check_timer(void) =20 static int mp_irqdomain_create(int ioapic) { - struct irq_domain *parent; + struct mp_ioapic_gsi *gsi_cfg =3D mp_ioapic_gsi_routing(ioapic); int hwirqs =3D mp_ioapic_pin_count(ioapic); struct ioapic *ip =3D &ioapics[ioapic]; struct ioapic_domain_cfg *cfg =3D &ip->irqdomain_cfg; - struct mp_ioapic_gsi *gsi_cfg =3D mp_ioapic_gsi_routing(ioapic); + struct irq_domain *parent; struct fwnode_handle *fn; struct irq_fwspec fwspec; =20 @@ -2367,10 +2252,8 @@ static int mp_irqdomain_create(int ioapic) return -ENOMEM; } =20 - if (cfg->type =3D=3D IOAPIC_DOMAIN_LEGACY || - cfg->type =3D=3D IOAPIC_DOMAIN_STRICT) - ioapic_dynirq_base =3D max(ioapic_dynirq_base, - gsi_cfg->gsi_end + 1); + if (cfg->type =3D=3D IOAPIC_DOMAIN_LEGACY || cfg->type =3D=3D IOAPIC_DOMAIN= _STRICT) + ioapic_dynirq_base =3D max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1); =20 return 0; } @@ -2397,13 +2280,11 @@ void __init setup_IO_APIC(void) =20 io_apic_irqs =3D nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; =20 - apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); + apic_pr_verbose("ENABLING IO-APIC IRQs\n"); for_each_ioapic(ioapic) BUG_ON(mp_irqdomain_create(ioapic)); =20 - /* - * Set up IO-APIC IRQ routing. - */ + /* Set up IO-APIC IRQ routing. */ x86_init.mpparse.setup_ioapic_ids(); =20 sync_Arb_IDs(); @@ -2417,16 +2298,14 @@ void __init setup_IO_APIC(void) =20 static void resume_ioapic_id(int ioapic_idx) { - unsigned long flags; union IO_APIC_reg_00 reg_00; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); reg_00.raw =3D io_apic_read(ioapic_idx, 0); if (reg_00.bits.ID !=3D mpc_ioapic_id(ioapic_idx)) { reg_00.bits.ID =3D mpc_ioapic_id(ioapic_idx); io_apic_write(ioapic_idx, 0, reg_00.raw); } - raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void ioapic_resume(void) @@ -2440,8 +2319,8 @@ static void ioapic_resume(void) } =20 static struct syscore_ops ioapic_syscore_ops =3D { - .suspend =3D save_ioapic_entries, - .resume =3D ioapic_resume, + .suspend =3D save_ioapic_entries, + .resume =3D ioapic_resume, }; =20 static int __init ioapic_init_ops(void) @@ -2456,15 +2335,13 @@ device_initcall(ioapic_init_ops); static int io_apic_get_redir_entries(int ioapic) { union IO_APIC_reg_01 reg_01; - unsigned long flags; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); reg_01.raw =3D io_apic_read(ioapic, 1); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 - /* The register returns the maximum index redir index - * supported, which is one less than the total number of redir - * entries. + /* + * The register returns the maximum index redir index supported, + * which is one less than the total number of redir entries. */ return reg_01.bits.entries + 1; } @@ -2494,16 +2371,14 @@ static int io_apic_get_unique_id(int ioapic, int apic= _id) static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC); const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; - unsigned long flags; int i =3D 0; =20 /* Initialize the ID map */ if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC)) copy_phys_cpu_present_map(apic_id_map); =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(ioapic, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) + reg_00.raw =3D io_apic_read(ioapic, 0); =20 if (apic_id >=3D broadcast_id) { pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n", @@ -2530,21 +2405,19 @@ static int io_apic_get_unique_id(int ioapic, int apic= _id) if (reg_00.bits.ID !=3D apic_id) { reg_00.bits.ID =3D apic_id; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(ioapic, 0, reg_00.raw); - reg_00.raw =3D io_apic_read(ioapic, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + io_apic_write(ioapic, 0, reg_00.raw); + reg_00.raw =3D io_apic_read(ioapic, 0); + } =20 /* Sanity check */ if (reg_00.bits.ID !=3D apic_id) { - pr_err("IOAPIC[%d]: Unable to change apic_id!\n", - ioapic); + pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); return -1; } } =20 - apic_printk(APIC_VERBOSE, KERN_INFO - "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); + apic_pr_verbose("IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); =20 return apic_id; } @@ -2560,7 +2433,6 @@ static u8 io_apic_unique_id(int idx, u8 id) { union IO_APIC_reg_00 reg_00; DECLARE_BITMAP(used, 256); - unsigned long flags; u8 new_id; int i; =20 @@ -2576,26 +2448,23 @@ static u8 io_apic_unique_id(int idx, u8 id) * Read the current id from the ioapic and keep it if * available. */ - raw_spin_lock_irqsave(&ioapic_lock, flags); - reg_00.raw =3D io_apic_read(idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) + reg_00.raw =3D io_apic_read(idx, 0); + new_id =3D reg_00.bits.ID; if (!test_bit(new_id, used)) { - apic_printk(APIC_VERBOSE, KERN_INFO - "IOAPIC[%d]: Using reg apic_id %d instead of %d\n", - idx, new_id, id); + apic_pr_verbose("IOAPIC[%d]: Using reg apic_id %d instead of %d\n", + idx, new_id, id); return new_id; } =20 - /* - * Get the next free id and write it to the ioapic. - */ + /* Get the next free id and write it to the ioapic. */ new_id =3D find_first_zero_bit(used, 256); reg_00.bits.ID =3D new_id; - raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(idx, 0, reg_00.raw); - reg_00.raw =3D io_apic_read(idx, 0); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); + scoped_guard (raw_spinlock_irqsave, &ioapic_lock) { + io_apic_write(idx, 0, reg_00.raw); + reg_00.raw =3D io_apic_read(idx, 0); + } /* Sanity check */ BUG_ON(reg_00.bits.ID !=3D new_id); =20 @@ -2605,12 +2474,10 @@ static u8 io_apic_unique_id(int idx, u8 id) =20 static int io_apic_get_version(int ioapic) { - union IO_APIC_reg_01 reg_01; - unsigned long flags; + union IO_APIC_reg_01 reg_01; =20 - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); reg_01.raw =3D io_apic_read(ioapic, 1); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 return reg_01.bits.version; } @@ -2625,8 +2492,8 @@ static struct resource *ioapic_resources; =20 static struct resource * __init ioapic_setup_resources(void) { - unsigned long n; struct resource *res; + unsigned long n; char *mem; int i; =20 @@ -2686,9 +2553,7 @@ void __init io_apic_init_mappings(void) ioapic_phys =3D mpc_ioapic_addr(i); #ifdef CONFIG_X86_32 if (!ioapic_phys) { - printk(KERN_ERR - "WARNING: bogus zero IO-APIC " - "address found in MPTABLE, " + pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, " "disabling IO/APIC support!\n"); smp_found_config =3D 0; ioapic_is_disabled =3D true; @@ -2707,9 +2572,8 @@ void __init io_apic_init_mappings(void) ioapic_phys =3D __pa(ioapic_phys); } io_apic_set_fixmap(idx, ioapic_phys); - apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", - __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), - ioapic_phys); + apic_pr_verbose("mapped IOAPIC to %08lx (%08lx)\n", + __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys); idx++; =20 ioapic_res->start =3D ioapic_phys; @@ -2720,13 +2584,12 @@ void __init io_apic_init_mappings(void) =20 void __init ioapic_insert_resources(void) { - int i; struct resource *r =3D ioapic_resources; + int i; =20 if (!r) { if (nr_ioapics > 0) - printk(KERN_ERR - "IO APIC resources couldn't be allocated.\n"); + pr_err("IO APIC resources couldn't be allocated.\n"); return; } =20 @@ -2746,11 +2609,12 @@ int mp_find_ioapic(u32 gsi) /* Find the IOAPIC that manages this GSI. */ for_each_ioapic(i) { struct mp_ioapic_gsi *gsi_cfg =3D mp_ioapic_gsi_routing(i); + if (gsi >=3D gsi_cfg->gsi_base && gsi <=3D gsi_cfg->gsi_end) return i; } =20 - printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); + pr_err("ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); return -1; } =20 @@ -2789,12 +2653,10 @@ static int bad_ioapic_register(int idx) =20 static int find_free_ioapic_entry(void) { - int idx; - - for (idx =3D 0; idx < MAX_IO_APICS; idx++) + for (int idx =3D 0; idx < MAX_IO_APICS; idx++) { if (ioapics[idx].nr_registers =3D=3D 0) return idx; - + } return MAX_IO_APICS; } =20 @@ -2805,8 +2667,7 @@ static int find_free_ioapic_entry(void) * @gsi_base: base of GSI associated with the IOAPIC * @cfg: configuration information for the IOAPIC */ -int mp_register_ioapic(int id, u32 address, u32 gsi_base, - struct ioapic_domain_cfg *cfg) +int mp_register_ioapic(int id, u32 address, u32 gsi_base, struct ioapic_doma= in_cfg *cfg) { bool hotplug =3D !!ioapic_initialized; struct mp_ioapic_gsi *gsi_cfg; @@ -2817,12 +2678,13 @@ int mp_register_ioapic(int id, u32 address, u32 gsi_b= ase, pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); return -EINVAL; } - for_each_ioapic(ioapic) + + for_each_ioapic(ioapic) { if (ioapics[ioapic].mp_config.apicaddr =3D=3D address) { - pr_warn("address 0x%x conflicts with IOAPIC%d\n", - address, ioapic); + pr_warn("address 0x%x conflicts with IOAPIC%d\n", address, ioapic); return -EEXIST; } + } =20 idx =3D find_free_ioapic_entry(); if (idx >=3D MAX_IO_APICS) { @@ -2857,8 +2719,7 @@ int mp_register_ioapic(int id, u32 address, u32 gsi_bas= e, (gsi_end >=3D gsi_cfg->gsi_base && gsi_end <=3D gsi_cfg->gsi_end)) { pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", - gsi_base, gsi_end, - gsi_cfg->gsi_base, gsi_cfg->gsi_end); + gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end); clear_fixmap(FIX_IO_APIC_BASE_0 + idx); return -ENOSPC; } @@ -2892,8 +2753,7 @@ int mp_register_ioapic(int id, u32 address, u32 gsi_bas= e, ioapics[idx].nr_registers =3D entries; =20 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", - idx, mpc_ioapic_id(idx), - mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), + idx, mpc_ioapic_id(idx), mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), gsi_cfg->gsi_base, gsi_cfg->gsi_end); =20 return 0; @@ -2904,11 +2764,13 @@ int mp_unregister_ioapic(u32 gsi_base) int ioapic, pin; int found =3D 0; =20 - for_each_ioapic(ioapic) + for_each_ioapic(ioapic) { if (ioapics[ioapic].gsi_config.gsi_base =3D=3D gsi_base) { found =3D 1; break; } + } + if (!found) { pr_warn("can't find IOAPIC for GSI %d\n", gsi_base); return -ENODEV; @@ -2922,8 +2784,7 @@ int mp_unregister_ioapic(u32 gsi_base) if (irq >=3D 0) { data =3D irq_get_chip_data(irq); if (data && data->count) { - pr_warn("pin%d on IOAPIC%d is still in use.\n", - pin, ioapic); + pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic); return -EBUSY; } } @@ -2958,8 +2819,7 @@ static void mp_irqdomain_get_attr(u32 gsi, struct mp_ch= ip_data *data, if (info && info->ioapic.valid) { data->is_level =3D info->ioapic.is_level; data->active_low =3D info->ioapic.active_low; - } else if (__acpi_get_override_irq(gsi, &data->is_level, - &data->active_low) < 0) { + } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_low)= < 0) { /* PCI interrupts are always active low level triggered. */ data->is_level =3D true; data->active_low =3D true; @@ -3017,10 +2877,8 @@ int mp_irqdomain_alloc(struct irq_domain *domain, unsi= gned int virq, return -ENOMEM; =20 ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); - if (ret < 0) { - kfree(data); - return ret; - } + if (ret < 0) + goto free_data; =20 INIT_LIST_HEAD(&data->irq_2_pin); irq_data->hwirq =3D info->ioapic.pin; @@ -3029,7 +2887,10 @@ int mp_irqdomain_alloc(struct irq_domain *domain, unsi= gned int virq, irq_data->chip_data =3D data; mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); =20 - add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); + if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)) { + ret =3D -ENOMEM; + goto free_irqs; + } =20 mp_preconfigure_entry(data); mp_register_handler(virq, data->is_level); @@ -3039,11 +2900,15 @@ int mp_irqdomain_alloc(struct irq_domain *domain, uns= igned int virq, legacy_pic->mask(virq); local_irq_restore(flags); =20 - apic_printk(APIC_VERBOSE, KERN_DEBUG - "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i Act= iveLow:%i)\n", - ioapic, mpc_ioapic_id(ioapic), pin, virq, - data->is_level, data->active_low); + apic_pr_verbose("IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d L= evel:%i ActiveLow:%i)\n", + ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_lo= w); return 0; + +free_irqs: + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +free_data: + kfree(data); + return ret; } =20 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq, @@ -3056,22 +2921,17 @@ void mp_irqdomain_free(struct irq_domain *domain, uns= igned int virq, irq_data =3D irq_domain_get_irq_data(domain, virq); if (irq_data && irq_data->chip_data) { data =3D irq_data->chip_data; - __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), - (int)irq_data->hwirq); + __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data= ->hwirq); WARN_ON(!list_empty(&data->irq_2_pin)); kfree(irq_data->chip_data); } irq_domain_free_irqs_top(domain, virq, nr_irqs); } =20 -int mp_irqdomain_activate(struct irq_domain *domain, - struct irq_data *irq_data, bool reserve) +int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_da= ta, bool reserve) { - unsigned long flags; - - raw_spin_lock_irqsave(&ioapic_lock, flags); + guard(raw_spinlock_irqsave)(&ioapic_lock); ioapic_configure_entry(irq_data); - raw_spin_unlock_irqrestore(&ioapic_lock, flags); return 0; } =20 @@ -3079,8 +2939,7 @@ void mp_irqdomain_deactivate(struct irq_domain *domain, struct irq_data *irq_data) { /* It won't be called for IRQ with multiple IOAPIC pins associated */ - ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), - (int)irq_data->hwirq); + ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq); } =20 int mp_irqdomain_ioapic_idx(struct irq_domain *domain) diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index e89171b0347a..4a1b1b28abf9 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -68,7 +68,7 @@ static void __init mpc_oem_bus_info(struct mpc_bus *m, char= *str) { memcpy(str, m->bustype, 6); str[6] =3D 0; - apic_printk(APIC_VERBOSE, "Bus #%d is %s\n", m->busid, str); + apic_pr_verbose("Bus #%d is %s\n", m->busid, str); } =20 static void __init MP_bus_info(struct mpc_bus *m) @@ -417,7 +417,7 @@ static unsigned long __init get_mpc_size(unsigned long ph= ysptr) mpc =3D early_memremap(physptr, PAGE_SIZE); size =3D mpc->length; early_memunmap(mpc, PAGE_SIZE); - apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); + apic_pr_verbose(" mpc: %lx-%lx\n", physptr, physptr + size); =20 return size; } @@ -560,8 +560,7 @@ static int __init smp_scan_config(unsigned long base, uns= igned long length) struct mpf_intel *mpf; int ret =3D 0; =20 - apic_printk(APIC_VERBOSE, "Scan for SMP in [mem %#010lx-%#010lx]\n", - base, base + length - 1); + apic_pr_verbose("Scan for SMP in [mem %#010lx-%#010lx]\n", base, base + len= gth - 1); BUILD_BUG_ON(sizeof(*mpf) !=3D 16); =20 while (length > 0) { @@ -683,13 +682,13 @@ static void __init check_irq_src(struct mpc_intsrc *m, = int *nr_m_spare) { int i; =20 - apic_printk(APIC_VERBOSE, "OLD "); + apic_pr_verbose("OLD "); print_mp_irq_info(m); =20 i =3D get_MP_intsrc_index(m); if (i > 0) { memcpy(m, &mp_irqs[i], sizeof(*m)); - apic_printk(APIC_VERBOSE, "NEW "); + apic_pr_verbose("NEW "); print_mp_irq_info(&mp_irqs[i]); return; } @@ -772,7 +771,7 @@ static int __init replace_intsrc_all(struct mpc_table *m= pc, continue; =20 if (nr_m_spare > 0) { - apic_printk(APIC_VERBOSE, "*NEW* found\n"); + apic_pr_verbose("*NEW* found\n"); nr_m_spare--; memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i])); m_spare[nr_m_spare] =3D NULL; diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_re= mapping.c index e090ca07364b..7a6d188e3bea 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1352,12 +1352,11 @@ static void intel_irq_remapping_prepare_irte(struct i= ntel_ir_data *data, case X86_IRQ_ALLOC_TYPE_IOAPIC: /* Set source-id of interrupt request */ set_ioapic_sid(irte, info->devid); - apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD= :%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X= Dest:%08X SID:%04X SQ:%X SVT:%X)\n", - info->devid, irte->present, irte->fpd, - irte->dst_mode, irte->redir_hint, - irte->trigger_mode, irte->dlvry_mode, - irte->avail, irte->vector, irte->dest_id, - irte->sid, irte->sq, irte->svt); + apic_pr_verbose("IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir= _hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X S= Q:%X SVT:%X)\n", + info->devid, irte->present, irte->fpd, irte->dst_mode, + irte->redir_hint, irte->trigger_mode, irte->dlvry_mode, + irte->avail, irte->vector, irte->dest_id, irte->sid, + irte->sq, irte->svt); sub_handle =3D info->ioapic.pin; break; case X86_IRQ_ALLOC_TYPE_HPET: . Subject: [GIT pull] x86/misc for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 10:54:14 +0200 (CEST) Linus, please pull the latest x86/misc branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-misc-2024-09= -17 up to: 4460e8538ef1: MAINTAINERS: Add selftests/x86 entry Miscellaneous updates for x86: - Rework kcpuid to handle the the autogenerated CSV file correctly and update the CSV file to cover the whole zoo of CPUID. - Avoid memcpy() for ia32 syscall_get_arguments() and use direct assignments as fortified memcpy() is unhappy about writing/reading beyond the end of the addresses destination/source struct member - A few new PCI IDs for AMD - Update MAINTAINERS to cover x86 specific selftests Thanks, tglx ------------------> Ahmed S. Darwish (9): tools/x86/kcpuid: Remove unused variable tools/x86/kcpuid: Properly align long-description columns tools/x86/kcpuid: Set max possible subleaves count to 64 tools/x86/kcpuid: Protect against faulty "max subleaf" values tools/x86/kcpuid: Strip bitfield names leading/trailing whitespace tools/x86/kcpuid: Recognize all leaves with subleaves tools/x86/kcpuid: Parse subleaf ranges if provided tools/x86/kcpuid: Introduce a complete cpuid bitfields CSV file MAINTAINERS: Add x86 cpuid database entry Kees Cook (1): x86/syscall: Avoid memcpy() for ia32 syscall_get_arguments() Muhammad Usama Anjum (1): MAINTAINERS: Add selftests/x86 entry Richard Gong (1): x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h-70h Shyam Sundar S K (1): x86/amd_nb: Add new PCI IDs for AMD family 1Ah model 60h MAINTAINERS | 11 + arch/x86/include/asm/syscall.h | 7 +- arch/x86/kernel/amd_nb.c | 7 + drivers/hwmon/k10temp.c | 1 + include/linux/pci_ids.h | 1 + tools/arch/x86/kcpuid/cpuid.csv | 1430 +++++++++++++++++++++++++++----------= -- tools/arch/x86/kcpuid/kcpuid.c | 109 +-- 7 files changed, 1100 insertions(+), 466 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 42decde38320..7715a806c255 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24772,6 +24772,17 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git= /tip/tip.git x86/core F: Documentation/arch/x86/ F: Documentation/devicetree/bindings/x86/ F: arch/x86/ +F: tools/testing/selftests/x86 + +X86 CPUID DATABASE +M: Borislav Petkov +M: Thomas Gleixner +M: x86@kernel.org +R: Ahmed S. Darwish +L: x86-cpuid@lists.linux.dev +S: Maintained +W: https://x86-cpuid.org +F: tools/arch/x86/kcpuid/cpuid.csv =20 X86 ENTRY CODE M: Andy Lutomirski diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h index 2fc7bc3863ff..7c488ff0c764 100644 --- a/arch/x86/include/asm/syscall.h +++ b/arch/x86/include/asm/syscall.h @@ -82,7 +82,12 @@ static inline void syscall_get_arguments(struct task_struc= t *task, struct pt_regs *regs, unsigned long *args) { - memcpy(args, ®s->bx, 6 * sizeof(args[0])); + args[0] =3D regs->bx; + args[1] =3D regs->cx; + args[2] =3D regs->dx; + args[3] =3D regs->si; + args[4] =3D regs->di; + args[5] =3D regs->bp; } =20 static inline int syscall_get_arch(struct task_struct *task) diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 059e5c16af05..dc5d3216af24 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -26,6 +26,7 @@ #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8 #define PCI_DEVICE_ID_AMD_1AH_M00H_ROOT 0x153a #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 +#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 #define PCI_DEVICE_ID_AMD_MI200_ROOT 0x14bb #define PCI_DEVICE_ID_AMD_MI300_ROOT 0x14f8 =20 @@ -43,6 +44,8 @@ #define PCI_DEVICE_ID_AMD_19H_M70H_DF_F4 0x14f4 #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F4 0x12fc #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4 0x12c4 +#define PCI_DEVICE_ID_AMD_1AH_M60H_DF_F4 0x124c +#define PCI_DEVICE_ID_AMD_1AH_M70H_DF_F4 0x12bc #define PCI_DEVICE_ID_AMD_MI200_DF_F4 0x14d4 #define PCI_DEVICE_ID_AMD_MI300_DF_F4 0x152c =20 @@ -63,6 +66,7 @@ static const struct pci_device_id amd_root_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M70H_ROOT) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_ROOT) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_ROOT) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_ROOT) }, {} @@ -95,6 +99,7 @@ static const struct pci_device_id amd_nb_misc_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F3) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_DF_F3) }, @@ -122,6 +127,8 @@ static const struct pci_device_id amd_nb_link_ids[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F4) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M70H_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI200_DF_F4) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_MI300_DF_F4) }, {} diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 543526bac042..f96b91e43312 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -548,6 +548,7 @@ static const struct pci_device_id k10temp_id_table[] =3D { { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3) }, { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, {} }; diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index e388c8b1cbc2..91182aa1d2ec 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -580,6 +580,7 @@ #define PCI_DEVICE_ID_AMD_19H_M78H_DF_F3 0x12fb #define PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3 0x12c3 #define PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3 0x16fb +#define PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3 0x124b #define PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3 0x12bb #define PCI_DEVICE_ID_AMD_MI200_DF_F3 0x14d3 #define PCI_DEVICE_ID_AMD_MI300_DF_F3 0x152b diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv index e0c25b75327e..d751eb8585d0 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,451 +1,1053 @@ -# The basic row format is: -# LEAF, SUBLEAF, register_name, bits, short_name, long_description - -# Leaf 00H - 0, 0, EAX, 31:0, max_basic_leafs, Max input value for support= ed subleafs - -# Leaf 01H - 1, 0, EAX, 3:0, stepping, Stepping ID - 1, 0, EAX, 7:4, model, Model - 1, 0, EAX, 11:8, family, Family ID - 1, 0, EAX, 13:12, processor, Processor Type - 1, 0, EAX, 19:16, model_ext, Extended Model ID - 1, 0, EAX, 27:20, family_ext, Extended Family ID - - 1, 0, EBX, 7:0, brand, Brand Index - 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) = in bytes - 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logi= c cpu in this package - 1, 0, EBX, 31:24, apic_id, Initial APIC ID - - 1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3) - 1, 0, ECX, 1, pclmulqdq, PCLMULQDQ instruction supported - 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout - 1, 0, ECX, 3, mwait, MONITOR/MWAIT supported - 1, 0, ECX, 4, ds_cpl, CPL Qualified Debug Store which allo= ws for branch message storage qualified by CPL - 1, 0, ECX, 5, vmx, Virtual Machine Extensions supported - 1, 0, ECX, 6, smx, Safer Mode Extension supported - 1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology - 1, 0, ECX, 8, tm2, Thermal Monitor 2 - 1, 0, ECX, 9, ssse3, Supplemental Streaming SIMD Extension= s 3 (SSSE3) - 1, 0, ECX, 10, l1_ctx_id, L1 data cache could be set to eit= her adaptive mode or shared mode (check IA32_MISC_ENABLE bit 24 definition) - 1, 0, ECX, 11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon d= ebug supported - 1, 0, ECX, 12, fma, FMA extensions using YMM state supported - 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchan= ge Bytes' supported - 1, 0, ECX, 14, xtpr_update, xTPR Update Control supported - 1, 0, ECX, 15, pdcm, Perfmon and Debug Capability present - 1, 0, ECX, 17, pcid, Process-Context Identifiers feature pr= esent - 1, 0, ECX, 18, dca, Prefetching data from a memory mapped d= evice supported - 1, 0, ECX, 19, sse4_1, SSE4.1 feature present - 1, 0, ECX, 20, sse4_2, SSE4.2 feature present - 1, 0, ECX, 21, x2apic, x2APIC supported - 1, 0, ECX, 22, movbe, MOVBE instruction supported - 1, 0, ECX, 23, popcnt, POPCNT instruction supported - 1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot = operation using a TSC deadline value - 1, 0, ECX, 25, aesni, AESNI instruction supported - 1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended state= s (XSETBV/XGETBV/XCR0) - 1, 0, ECX, 27, osxsave, OS has set CR4.OSXSAVE bit to enabl= e XSETBV/XGETBV/XCR0 - 1, 0, ECX, 28, avx, AVX instruction supported - 1, 0, ECX, 29, f16c, 16-bit floating-point conversion instr= uction supported - 1, 0, ECX, 30, rdrand, RDRAND instruction supported - - 1, 0, EDX, 0, fpu, x87 FPU on chip - 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement - 1, 0, EDX, 2, de, Debugging Extensions - 1, 0, EDX, 3, pse, Page Size Extensions - 1, 0, EDX, 4, tsc, Time Stamp Counter - 1, 0, EDX, 5, msr, RDMSR and WRMSR Support - 1, 0, EDX, 6, pae, Physical Address Extensions - 1, 0, EDX, 7, mce, Machine Check Exception - 1, 0, EDX, 8, cx8, CMPXCHG8B instr - 1, 0, EDX, 9, apic, APIC on Chip - 1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs - 1, 0, EDX, 12, mtrr, Memory Type Range Registers - 1, 0, EDX, 13, pge, Page Global Bit - 1, 0, EDX, 14, mca, Machine Check Architecture - 1, 0, EDX, 15, cmov, Conditional Move Instrs - 1, 0, EDX, 16, pat, Page Attribute Table - 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension - 1, 0, EDX, 18, psn, Processor Serial Number - 1, 0, EDX, 19, clflush, CLFLUSH instr -# 1, 0, EDX, 20, - 1, 0, EDX, 21, ds, Debug Store - 1, 0, EDX, 22, acpi, Thermal Monitor and Software Controlle= d Clock Facilities - 1, 0, EDX, 23, mmx, Intel MMX Technology - 1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs - 1, 0, EDX, 25, sse, SSE - 1, 0, EDX, 26, sse2, SSE2 - 1, 0, EDX, 27, ss, Self Snoop - 1, 0, EDX, 28, hit, Max APIC IDs - 1, 0, EDX, 29, tm, Thermal Monitor -# 1, 0, EDX, 30, - 1, 0, EDX, 31, pbe, Pending Break Enable - -# Leaf 02H -# cache and TLB descriptor info - -# Leaf 03H -# Precessor Serial Number, introduced on Pentium III, not valid for -# latest models - -# Leaf 04H -# thread/core and cache topology - 4, 0, EAX, 4:0, cache_type, Cache type like instr/data or un= ified - 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1) - 4, 0, EAX, 8, cache_self_init, Cache Self Initialization - 4, 0, EAX, 9, fully_associate, Fully Associative cache -# 4, 0, EAX, 13:10, resvd, resvd - 4, 0, EAX, 25:14, max_logical_id, Max number of addressable ID= s for logical processors sharing the cache - 4, 0, EAX, 31:26, max_phy_id, Max number of addressable IDs fo= r processors in phy package - - 4, 0, EBX, 11:0, cache_linesize, Size of a cache line in bytes - 4, 0, EBX, 21:12, cache_partition, Physical Line partitions - 4, 0, EBX, 31:22, cache_ways, Ways of associativity - 4, 0, ECX, 31:0, cache_sets, Number of Sets - 1 - 4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganrant= eed to act upon lower level caches of non-originating threads sharing this ca= che - 4, 0, EDX, 1, c_incl, Whether cache is inclusive of lower = cache level - 4, 0, EDX, 2, c_comp_index, Complex Cache Indexing - -# Leaf 05H -# MONITOR/MWAIT - 5, 0, EAX, 15:0, min_mon_size, Smallest monitor line size in bytes - 5, 0, EBX, 15:0, max_mon_size, Largest monitor line size in bytes - 5, 0, ECX, 0, mwait_ext, Enum of Monitor-Mwait extensions support= ed - 5, 0, ECX, 1, mwait_irq_break, Largest monitor line size in bytes - 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supported = using MWAIT - 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supported = using MWAIT - 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supported = using MWAIT - 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supported = using MWAIT - 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supported = using MWAIT - 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported = using MWAIT - 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supported = using MWAIT - 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supported = using MWAIT - -# Leaf 06H -# Thermal & Power Management - - 6, 0, EAX, 0, dig_temp, Digital temperature sensor supported - 6, 0, EAX, 1, turbo, Intel Turbo Boost - 6, 0, EAX, 2, arat, Always running APIC timer -# 6, 0, EAX, 3, resv, Reserved - 6, 0, EAX, 4, pln, Power limit notifications supported - 6, 0, EAX, 5, ecmd, Clock modulation duty cycle extension support= ed - 6, 0, EAX, 6, ptm, Package thermal management supported - 6, 0, EAX, 7, hwp, HWP base register - 6, 0, EAX, 8, hwp_notify, HWP notification - 6, 0, EAX, 9, hwp_act_window, HWP activity window - 6, 0, EAX, 10, hwp_energy, HWP energy performance preference - 6, 0, EAX, 11, hwp_pkg_req, HWP package level request -# 6, 0, EAX, 12, resv, Reserved - 6, 0, EAX, 13, hdc, HDC base registers supported - 6, 0, EAX, 14, turbo3, Turbo Boost Max 3.0 - 6, 0, EAX, 15, hwp_cap, Highest Performance change supported - 6, 0, EAX, 16, hwp_peci, HWP PECI override is supported - 6, 0, EAX, 17, hwp_flex, Flexible HWP is supported - 6, 0, EAX, 18, hwp_fast, Fast access mode for the IA32_HWP_REQUEST= MSR is supported -# 6, 0, EAX, 19, resv, Reserved - 6, 0, EAX, 20, hwp_ignr, Ignoring Idle Logical Processor HWP reque= st is supported - - 6, 0, EBX, 3:0, therm_irq_thresh, Number of Interrupt Thresholds in= Digital Thermal Sensor - 6, 0, ECX, 0, aperfmperf, Presence of IA32_MPERF and IA32_APERF - 6, 0, ECX, 3, energ_bias, Performance-energy bias preference supp= orted - -# Leaf 07H -# ECX =3D=3D 0 -# AVX512 refers to https://en.wikipedia.org/wiki/AVX-512 -# XXX: Do we really need to enumerate each and every AVX512 sub features - - 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE suppo= rted - 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported - 7, 0, EBX, 2, sgx, Software Guard Extensions - 7, 0, EBX, 3, bmi1, BMI1 - 7, 0, EBX, 4, hle, Hardware Lock Elision - 7, 0, EBX, 5, avx2, AVX2 -# 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only o= n x87 exceptions - 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention - 7, 0, EBX, 8, bmi2, BMI2 - 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB - 7, 0, EBX, 10, invpcid, INVPCID instruction - 7, 0, EBX, 11, rtm, Restricted Transactional Memory - 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability - 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS - 7, 0, EBX, 14, mpx, Memory Protection Extensions - 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability - 7, 0, EBX, 16, avx512f, AVX512 Foundation instr - 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr - 7, 0, EBX, 18, rdseed, RDSEED instr - 7, 0, EBX, 19, adx, ADX instr - 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention - 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add -# 7, 0, EBX, 22, resvd, resvd - 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr - 7, 0, EBX, 24, clwb, CLWB instr - 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr - 7, 0, EBX, 26, avx512pf, Prefetch - 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr - 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr - 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr - 7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr - 7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL) - 7, 0, ECX, 0, prefetchwt1, X - 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instruc= tions - 7, 0, ECX, 2, umip, User-mode Instruction Prevention - - 7, 0, ECX, 3, pku, Protection Keys for User-mode pages - 7, 0, ECX, 4, ospke, CR4 PKE set to enable protection keys -# 7, 0, ECX, 16:5, resvd, resvd - 7, 0, ECX, 21:17, mawau, The value of MAWAU used by the BNDLDX and BN= DSTX instructions in 64-bit mode - 7, 0, ECX, 22, rdpid, RDPID and IA32_TSC_AUX -# 7, 0, ECX, 29:23, resvd, resvd - 7, 0, ECX, 30, sgx_lc, SGX Launch Configuration -# 7, 0, ECX, 31, resvd, resvd - -# Leaf 08H -# - - -# Leaf 09H -# Direct Cache Access (DCA) information - 9, 0, ECX, 31:0, dca_cap, The value of IA32_PLATFORM_DCA_CAP +# SPDX-License-Identifier: CC0-1.0 +# Generator: x86-cpuid-db v1.0 =20 -# Leaf 0AH -# Architectural Performance Monitoring # -# Do we really need to print out the PMU related stuff? -# Does normal user really care about it? +# Auto-generated file. +# Please submit all updates and bugfixes to https://x86-cpuid.org # - 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version - 0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PMU = counters per logical CPU - 0xA, 0, EAX, 23:16, pmu_cnt_bits, Bit wideth of PMU counter - 0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to en= umerate PMU events - - 0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event not = available - 0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired ev= ent not available - 0xA, 0, EBX, 2, pmu_no_ref_cycle_evt, Reference cycles event= not available - 0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache referen= ce event not available - 0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misses = event not available - 0xA, 0, EBX, 5, pmu_no_br_instr_ret_evt, Branch instruction = retired event not available - 0xA, 0, EBX, 6, pmu_no_br_mispredict_evt, Branch mispredict = retired event not available - - 0xA, 0, ECX, 4:0, pmu_fixed_cnt_num, Performance Monitoring Un= it version - 0xA, 0, ECX, 12:5, pmu_fixed_cnt_bits, Numer of PMU counters pe= r logical CPU - -# Leaf 0BH -# Extended Topology Enumeration Leaf -# - - 0xB, 0, EAX, 4:0, id_shift, Number of bits to shift right on x= 2APIC ID to get a unique topology ID of the next level type - 0xB, 0, EBX, 15:0, cpu_nr, Number of logical processors at this= level type - 0xB, 0, ECX, 15:8, lvl_type, 0-Invalid 1-SMT 2-Core - 0xB, 0, EDX, 31:0, x2apic_id, x2APIC ID the current logical pro= cessor - - -# Leaf 0DH -# Processor Extended State =20 - 0xD, 0, EAX, 0, x87, X87 state - 0xD, 0, EAX, 1, sse, SSE state - 0xD, 0, EAX, 2, avx, AVX state - 0xD, 0, EAX, 4:3, mpx, MPX state - 0xD, 0, EAX, 7:5, avx512, AVX-512 state - 0xD, 0, EAX, 9, pkru, PKRU state - - 0xD, 0, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required b= y enabled features in XCR0 - 0xD, 0, ECX, 31:0, max_sz_xsave, Maximum size (bytes) of the XS= AVE/XRSTOR save area - - 0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available - 0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported - 0xD, 1, EAX, 2, xgetbv, XGETBV supported - 0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS supported - - 0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required b= y enabled features in XCR0 - 0xD, 1, ECX, 8, pt, PT state - 0xD, 1, ECX, 11, cet_usr, CET user state - 0xD, 1, ECX, 12, cet_supv, CET supervisor state - 0xD, 1, ECX, 13, hdc, HDC state - 0xD, 1, ECX, 16, hwp, HWP state - -# Leaf 0FH -# Intel RDT Monitoring - - 0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of RM= ID within this physical processor of all types - 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring support= ed - - 0xF, 1, ECX, 31:0, rmid_range, Maximum range (zero-based) of RM= ID of this types - 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring s= upported - 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monito= ring supported - 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monito= ring supported +# The basic row format is: +# LEAF, SUBLEAVES, reg, bits, short_name , long_descr= iption + +# Leaf 0H +# Maximum standard leaf number + CPU vendor string + + 0, 0, eax, 31:0, max_std_leaf , Highest cp= uid standard leaf supported + 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor= ID string bytes 0 - 3 + 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor= ID string bytes 8 - 11 + 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor= ID string bytes 4 - 7 + +# Leaf 1H +# CPU FMS (Family/Model/Stepping) + standard feature flags + + 1, 0, eax, 3:0, stepping , Stepping ID + 1, 0, eax, 7:4, base_model , Base CPU m= odel ID + 1, 0, eax, 11:8, base_family_id , Base CPU f= amily ID + 1, 0, eax, 13:12, cpu_type , CPU type + 1, 0, eax, 19:16, ext_model , Extended C= PU model ID + 1, 0, eax, 27:20, ext_family , Extended C= PU family ID + 1, 0, ebx, 7:0, brand_id , Brand index + 1, 0, ebx, 15:8, clflush_size , CLFLUSH in= struction cache line size + 1, 0, ebx, 23:16, n_logical_cpu , Logical CP= U (HW threads) count + 1, 0, ebx, 31:24, local_apic_id , Initial lo= cal APIC physical ID + 1, 0, ecx, 0, pni , Streaming = SIMD Extensions 3 (SSE3) + 1, 0, ecx, 1, pclmulqdq , PCLMULQDQ = instruction support + 1, 0, ecx, 2, dtes64 , 64-bit DS = save area + 1, 0, ecx, 3, monitor , MONITOR/MW= AIT support + 1, 0, ecx, 4, ds_cpl , CPL Qualif= ied Debug Store + 1, 0, ecx, 5, vmx , Virtual Ma= chine Extensions + 1, 0, ecx, 6, smx , Safer Mode= Extensions + 1, 0, ecx, 7, est , Enhanced I= ntel SpeedStep + 1, 0, ecx, 8, tm2 , Thermal Mo= nitor 2 + 1, 0, ecx, 9, ssse3 , Supplement= al SSE3 + 1, 0, ecx, 10, cid , L1 Context= ID + 1, 0, ecx, 11, sdbg , Sillicon D= ebug + 1, 0, ecx, 12, fma , FMA extens= ions using YMM state + 1, 0, ecx, 13, cx16 , CMPXCHG16B= instruction support + 1, 0, ecx, 14, xtpr , xTPR Updat= e Control + 1, 0, ecx, 15, pdcm , Perfmon an= d Debug Capability + 1, 0, ecx, 17, pcid , Process-co= ntext identifiers + 1, 0, ecx, 18, dca , Direct Cac= he Access + 1, 0, ecx, 19, sse4_1 , SSE4.1 + 1, 0, ecx, 20, sse4_2 , SSE4.2 + 1, 0, ecx, 21, x2apic , X2APIC sup= port + 1, 0, ecx, 22, movbe , MOVBE inst= ruction support + 1, 0, ecx, 23, popcnt , POPCNT ins= truction support + 1, 0, ecx, 24, tsc_deadline_timer , APIC timer= one-shot operation + 1, 0, ecx, 25, aes , AES instru= ctions + 1, 0, ecx, 26, xsave , XSAVE (and= related instructions) support + 1, 0, ecx, 27, osxsave , XSAVE (and= related instructions) are enabled by OS + 1, 0, ecx, 28, avx , AVX instru= ctions support + 1, 0, ecx, 29, f16c , Half-preci= sion floating-point conversion support + 1, 0, ecx, 30, rdrand , RDRAND ins= truction support + 1, 0, ecx, 31, guest_status , System is = running as guest; (para-)virtualized system + 1, 0, edx, 0, fpu , Floating-P= oint Unit on-chip (x87) + 1, 0, edx, 1, vme , Virtual-80= 86 Mode Extensions + 1, 0, edx, 2, de , Debugging = Extensions + 1, 0, edx, 3, pse , Page Size = Extension + 1, 0, edx, 4, tsc , Time Stamp= Counter + 1, 0, edx, 5, msr , Model-Spec= ific Registers (RDMSR and WRMSR support) + 1, 0, edx, 6, pae , Physical A= ddress Extensions + 1, 0, edx, 7, mce , Machine Ch= eck Exception + 1, 0, edx, 8, cx8 , CMPXCHG8B = instruction + 1, 0, edx, 9, apic , APIC on-ch= ip + 1, 0, edx, 11, sep , SYSENTER, = SYSEXIT, and associated MSRs + 1, 0, edx, 12, mtrr , Memory Typ= e Range Registers + 1, 0, edx, 13, pge , Page Globa= l Extensions + 1, 0, edx, 14, mca , Machine Ch= eck Architecture + 1, 0, edx, 15, cmov , Conditiona= l Move Instruction + 1, 0, edx, 16, pat , Page Attri= bute Table + 1, 0, edx, 17, pse36 , Page Size = Extension (36-bit) + 1, 0, edx, 18, pn , Processor = Serial Number + 1, 0, edx, 19, clflush , CLFLUSH in= struction + 1, 0, edx, 21, dts , Debug Store + 1, 0, edx, 22, acpi , Thermal mo= nitor and clock control + 1, 0, edx, 23, mmx , MMX instru= ctions + 1, 0, edx, 24, fxsr , FXSAVE and= FXRSTOR instructions + 1, 0, edx, 25, sse , SSE instru= ctions + 1, 0, edx, 26, sse2 , SSE2 instr= uctions + 1, 0, edx, 27, ss , Self Snoop + 1, 0, edx, 28, ht , Hyper-thre= ading + 1, 0, edx, 29, tm , Thermal Mo= nitor + 1, 0, edx, 30, ia64 , Legacy IA-= 64 (Itanium) support bit, now resreved + 1, 0, edx, 31, pbe , Pending Br= eak Enable + +# Leaf 2H +# Intel cache and TLB information one-byte descriptors + + 2, 0, eax, 7:0, iteration_count , Number of = times this CPUD leaf must be queried + 2, 0, eax, 15:8, desc1 , Descriptor= #1 + 2, 0, eax, 23:16, desc2 , Descriptor= #2 + 2, 0, eax, 30:24, desc3 , Descriptor= #3 + 2, 0, eax, 31, eax_invalid , Descriptor= s 1-3 are invalid if set + 2, 0, ebx, 7:0, desc4 , Descriptor= #4 + 2, 0, ebx, 15:8, desc5 , Descriptor= #5 + 2, 0, ebx, 23:16, desc6 , Descriptor= #6 + 2, 0, ebx, 30:24, desc7 , Descriptor= #7 + 2, 0, ebx, 31, ebx_invalid , Descriptor= s 4-7 are invalid if set + 2, 0, ecx, 7:0, desc8 , Descriptor= #8 + 2, 0, ecx, 15:8, desc9 , Descriptor= #9 + 2, 0, ecx, 23:16, desc10 , Descriptor= #10 + 2, 0, ecx, 30:24, desc11 , Descriptor= #11 + 2, 0, ecx, 31, ecx_invalid , Descriptor= s 8-11 are invalid if set + 2, 0, edx, 7:0, desc12 , Descriptor= #12 + 2, 0, edx, 15:8, desc13 , Descriptor= #13 + 2, 0, edx, 23:16, desc14 , Descriptor= #14 + 2, 0, edx, 30:24, desc15 , Descriptor= #15 + 2, 0, edx, 31, edx_invalid , Descriptor= s 12-15 are invalid if set + +# Leaf 4H +# Intel deterministic cache parameters + + 4, 31:0, eax, 4:0, cache_type , Cache type= field + 4, 31:0, eax, 7:5, cache_level , Cache leve= l (1-based) + 4, 31:0, eax, 8, cache_self_init , Self-initi= alializing cache level + 4, 31:0, eax, 9, fully_associative , Fully-asso= ciative cache + 4, 31:0, eax, 25:14, num_threads_sharing , Number log= ical CPUs sharing this cache + 4, 31:0, eax, 31:26, num_cores_on_die , Number of = cores in the physical package + 4, 31:0, ebx, 11:0, cache_linesize , System coh= erency line size (0-based) + 4, 31:0, ebx, 21:12, cache_npartitions , Physical l= ine partitions (0-based) + 4, 31:0, ebx, 31:22, cache_nways , Ways of as= sociativity (0-based) + 4, 31:0, ecx, 30:0, cache_nsets , Cache numb= er of sets (0-based) + 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INV= D not guaranteed for Remote Lower-Level caches + 4, 31:0, edx, 1, ll_inclusive , Cache is i= nclusive of Lower-Level caches + 4, 31:0, edx, 2, complex_indexing , Not a dire= ct-mapped cache (complex function) + +# Leaf 5H +# MONITOR/MWAIT instructions enumeration + + 5, 0, eax, 15:0, min_mon_size , Smallest m= onitor-line size, in bytes + 5, 0, ebx, 15:0, max_mon_size , Largest mo= nitor-line size, in bytes + 5, 0, ecx, 0, mwait_ext , Enumeratio= n of MONITOR/MWAIT extensions is supported + 5, 0, ecx, 1, mwait_irq_break , Interrupts= as a break-event for MWAIT is supported + 5, 0, edx, 3:0, n_c0_substates , Number of = C0 sub C-states supported using MWAIT + 5, 0, edx, 7:4, n_c1_substates , Number of = C1 sub C-states supported using MWAIT + 5, 0, edx, 11:8, n_c2_substates , Number of = C2 sub C-states supported using MWAIT + 5, 0, edx, 15:12, n_c3_substates , Number of = C3 sub C-states supported using MWAIT + 5, 0, edx, 19:16, n_c4_substates , Number of = C4 sub C-states supported using MWAIT + 5, 0, edx, 23:20, n_c5_substates , Number of = C5 sub C-states supported using MWAIT + 5, 0, edx, 27:24, n_c6_substates , Number of = C6 sub C-states supported using MWAIT + 5, 0, edx, 31:28, n_c7_substates , Number of = C7 sub C-states supported using MWAIT + +# Leaf 6H +# Thermal and Power Management enumeration + + 6, 0, eax, 0, dtherm , Digital te= mprature sensor + 6, 0, eax, 1, turbo_boost , Intel Turb= o Boost + 6, 0, eax, 2, arat , Always-Run= ning APIC Timer (not affected by p-state) + 6, 0, eax, 4, pln , Power Limi= t Notification (PLN) event + 6, 0, eax, 5, ecmd , Clock modu= lation duty cycle extension + 6, 0, eax, 6, pts , Package th= ermal management + 6, 0, eax, 7, hwp , HWP (Hardw= are P-states) base registers are supported + 6, 0, eax, 8, hwp_notify , HWP notifi= cation (IA32_HWP_INTERRUPT MSR) + 6, 0, eax, 9, hwp_act_window , HWP activi= ty window (IA32_HWP_REQUEST[bits 41:32]) supported + 6, 0, eax, 10, hwp_epp , HWP Energy= Performance Preference + 6, 0, eax, 11, hwp_pkg_req , HWP Packag= e Level Request + 6, 0, eax, 13, hdc_base_regs , HDC base r= egisters are supported + 6, 0, eax, 14, turbo_boost_3_0 , Intel Turb= o Boost Max 3.0 + 6, 0, eax, 15, hwp_capabilities , HWP Highes= t Performance change + 6, 0, eax, 16, hwp_peci_override , HWP PECI o= verride + 6, 0, eax, 17, hwp_flexible , Flexible H= WP + 6, 0, eax, 18, hwp_fast , IA32_HWP_R= EQUEST MSR fast access mode + 6, 0, eax, 19, hfi , HW_FEEDBAC= K MSRs supported + 6, 0, eax, 20, hwp_ignore_idle , Ignoring i= dle logical CPU HWP req is supported + 6, 0, eax, 23, thread_director , Intel thre= ad director support + 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM= _INTERRUPT MSR bit 25 is supported + 6, 0, ebx, 3:0, n_therm_thresholds , Digital th= ermometer thresholds + 6, 0, ecx, 0, aperfmperf , MPERF/APER= F MSRs (effective frequency interface) + 6, 0, ecx, 3, epb , IA32_ENERG= Y_PERF_BIAS MSR support + 6, 0, ecx, 15:8, thrd_director_nclasses , Number of = classes, Intel thread director + 6, 0, edx, 0, perfcap_reporting , Performanc= e capability reporting + 6, 0, edx, 1, encap_reporting , Energy eff= iciency capability reporting + 6, 0, edx, 11:8, feedback_sz , HW feedbac= k interface struct size, in 4K pages + 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logic= al CPU index @ HW feedback struct, 0-based + +# Leaf 7H +# Extended CPU features enumeration + + 7, 0, eax, 31:0, leaf7_n_subleaves , Number of = cpuid 0x7 subleaves + 7, 0, ebx, 0, fsgsbase , FSBASE/GSB= ASE read/write support + 7, 0, ebx, 1, tsc_adjust , IA32_TSC_A= DJUST MSR supported + 7, 0, ebx, 2, sgx , Intel SGX = (Software Guard Extensions) + 7, 0, ebx, 3, bmi1 , Bit manipu= lation extensions group 1 + 7, 0, ebx, 4, hle , Hardware L= ock Elision + 7, 0, ebx, 5, avx2 , AVX2 instr= uction set + 7, 0, ebx, 6, fdp_excptn_only , FPU Data P= ointer updated only on x87 exceptions + 7, 0, ebx, 7, smep , Supervisor= Mode Execution Protection + 7, 0, ebx, 8, bmi2 , Bit manipu= lation extensions group 2 + 7, 0, ebx, 9, erms , Enhanced R= EP MOVSB/STOSB + 7, 0, ebx, 10, invpcid , INVPCID in= struction (Invalidate Processor Context ID) + 7, 0, ebx, 11, rtm , Intel rest= ricted transactional memory + 7, 0, ebx, 12, cqm , Intel RDT-= CMT / AMD Platform-QoS cache monitoring + 7, 0, ebx, 13, zero_fcs_fds , Deprecated= FPU CS/DS (stored as zero) + 7, 0, ebx, 14, mpx , Intel memo= ry protection extensions + 7, 0, ebx, 15, rdt_a , Intel RDT = / AMD Platform-QoS Enforcemeent + 7, 0, ebx, 16, avx512f , AVX-512 fo= undation instructions + 7, 0, ebx, 17, avx512dq , AVX-512 do= uble/quadword instructions + 7, 0, ebx, 18, rdseed , RDSEED ins= truction + 7, 0, ebx, 19, adx , ADCX/ADOX = instructions + 7, 0, ebx, 20, smap , Supervisor= mode access prevention + 7, 0, ebx, 21, avx512ifma , AVX-512 in= teger fused multiply add + 7, 0, ebx, 23, clflushopt , CLFLUSHOPT= instruction + 7, 0, ebx, 24, clwb , CLWB instr= uction + 7, 0, ebx, 25, intel_pt , Intel proc= essor trace + 7, 0, ebx, 26, avx512pf , AVX-512 pr= efetch instructions + 7, 0, ebx, 27, avx512er , AVX-512 ex= ponent/reciprocal instrs + 7, 0, ebx, 28, avx512cd , AVX-512 co= nflict detection instrs + 7, 0, ebx, 29, sha_ni , SHA/SHA256= instructions + 7, 0, ebx, 30, avx512bw , AVX-512 BW= (byte/word granular) instructions + 7, 0, ebx, 31, avx512vl , AVX-512 VL= (128/256 vector length) extensions + 7, 0, ecx, 0, prefetchwt1 , PREFETCHWT= 1 (Intel Xeon Phi only) + 7, 0, ecx, 1, avx512vbmi , AVX-512 Ve= ctor byte manipulation instrs + 7, 0, ecx, 2, umip , User mode = instruction protection + 7, 0, ecx, 3, pku , Protection= keys for user-space + 7, 0, ecx, 4, ospke , OS protect= ion keys enable + 7, 0, ecx, 5, waitpkg , WAITPKG in= structions + 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 ve= ctor byte manipulation instrs group 2 + 7, 0, ecx, 7, cet_ss , CET shadow= stack features + 7, 0, ecx, 8, gfni , Galois fie= ld new instructions + 7, 0, ecx, 9, vaes , Vector AES= instrs + 7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ= 256-bit instruction support + 7, 0, ecx, 11, avx512_vnni , Vector neu= ral network instructions + 7, 0, ecx, 12, avx512_bitalg , AVX-512 bi= t count/shiffle + 7, 0, ecx, 13, tme , Intel tota= l memory encryption + 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: P= OPCNT for vectors of DW/QW + 7, 0, ecx, 16, la57 , 57-bit lin= ear addreses (five-level paging) + 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BND= STX MAWAU value in 64-bit mode + 7, 0, ecx, 22, rdpid , RDPID inst= ruction + 7, 0, ecx, 23, key_locker , Intel key = locker support + 7, 0, ecx, 24, bus_lock_detect , OS bus-loc= k detection + 7, 0, ecx, 25, cldemote , CLDEMOTE i= nstruction + 7, 0, ecx, 27, movdiri , MOVDIRI in= struction + 7, 0, ecx, 28, movdir64b , MOVDIR64B = instruction + 7, 0, ecx, 29, enqcmd , Enqueue st= ores supported (ENQCMD{,S}) + 7, 0, ecx, 30, sgx_lc , Intel SGX = launch configuration + 7, 0, ecx, 31, pks , Protection= keys for supervisor-mode pages + 7, 0, edx, 1, sgx_keys , Intel SGX = attestation services + 7, 0, edx, 2, avx512_4vnniw , AVX-512 ne= ural network instructions + 7, 0, edx, 3, avx512_4fmaps , AVX-512 mu= ltiply accumulation single precision + 7, 0, edx, 4, fsrm , Fast short= REP MOV + 7, 0, edx, 5, uintr , CPU suppor= ts user interrupts + 7, 0, edx, 8, avx512_vp2intersect , VP2INTERSE= CT{D,Q} instructions + 7, 0, edx, 9, srdbs_ctrl , SRBDS miti= gation MSR available + 7, 0, edx, 10, md_clear , VERW MD_CL= EAR microcode support + 7, 0, edx, 11, rtm_always_abort , XBEGIN (RT= M transaction) always aborts + 7, 0, edx, 13, tsx_force_abort , MSR TSX_FO= RCE_ABORT, RTM_ABORT bit, supported + 7, 0, edx, 14, serialize , SERIALIZE = instruction + 7, 0, edx, 15, hybrid_cpu , The CPU is= identified as a 'hybrid part' + 7, 0, edx, 16, tsxldtrk , TSX suspen= d/resume load address tracking + 7, 0, edx, 18, pconfig , PCONFIG in= struction + 7, 0, edx, 19, arch_lbr , Intel arch= itectural LBRs + 7, 0, edx, 20, ibt , CET indire= ct branch tracking + 7, 0, edx, 22, amx_bf16 , AMX-BF16: = tile bfloat16 support + 7, 0, edx, 23, avx512_fp16 , AVX-512 FP= 16 instructions + 7, 0, edx, 24, amx_tile , AMX-TILE: = tile architecture support + 7, 0, edx, 25, amx_int8 , AMX-INT8: = tile 8-bit integer support + 7, 0, edx, 26, spec_ctrl , Speculatio= n Control (IBRS/IBPB: indirect branch restrictions) + 7, 0, edx, 27, intel_stibp , Single thr= ead indirect branch predictors + 7, 0, edx, 28, flush_l1d , FLUSH L1D = cache: IA32_FLUSH_CMD MSR + 7, 0, edx, 29, arch_capabilities , Intel IA32= _ARCH_CAPABILITIES MSR + 7, 0, edx, 30, core_capabilities , IA32_CORE_= CAPABILITIES MSR + 7, 0, edx, 31, spec_ctrl_ssbd , Speculativ= e store bypass disable + 7, 1, eax, 4, avx_vnni , AVX-VNNI i= nstructions + 7, 1, eax, 5, avx512_bf16 , AVX-512 bF= loat16 instructions + 7, 1, eax, 6, lass , Linear add= ress space separation + 7, 1, eax, 7, cmpccxadd , CMPccXADD = instructions + 7, 1, eax, 8, arch_perfmon_ext , ArchPerfmo= nExt: CPUID leaf 0x23 is supported + 7, 1, eax, 10, fzrm , Fast zero-= length REP MOVSB + 7, 1, eax, 11, fsrs , Fast short= REP STOSB + 7, 1, eax, 12, fsrc , Fast Short= REP CMPSB/SCASB + 7, 1, eax, 17, fred , FRED: Flex= ible return and event delivery transitions + 7, 1, eax, 18, lkgs , LKGS: Load= 'kernel' (userspace) GS + 7, 1, eax, 19, wrmsrns , WRMSRNS in= str (WRMSR-non-serializing) + 7, 1, eax, 21, amx_fp16 , AMX-FP16: = FP16 tile operations + 7, 1, eax, 22, hreset , History re= set support + 7, 1, eax, 23, avx_ifma , Integer fu= sed multiply add + 7, 1, eax, 26, lam , Linear add= ress masking + 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/= WRMSRLIST instructions + 7, 1, ebx, 0, intel_ppin , Protected = processor inventory number (PPIN{,_CTL} MSRs) + 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-I= NT8 instructions + 7, 1, edx, 5, avx_ne_convert , AVX-NE-CON= VERT instructions + 7, 1, edx, 8, amx_complex , AMX-COMPLE= X instructions (starting from Granite Rapids) + 7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT= 0/1 instructions + 7, 1, edx, 18, cet_sss , CET superv= isor shadow stacks safe to use + 7, 2, edx, 0, intel_psfd , Intel pred= ictive store forward disable + 7, 2, edx, 1, ipred_ctrl , MSR bits I= A32_SPEC_CTRL.IPRED_DIS_{U,S} + 7, 2, edx, 2, rrsba_ctrl , MSR bits I= A32_SPEC_CTRL.RRSBA_DIS_{U,S} + 7, 2, edx, 3, ddp_ctrl , MSR bit I= A32_SPEC_CTRL.DDPD_U + 7, 2, edx, 4, bhi_ctrl , MSR bit I= A32_SPEC_CTRL.BHI_DIS_S + 7, 2, edx, 5, mcdt_no , MCDT mitig= ation not needed + 7, 2, edx, 6, uclock_disable , UC-lock di= sable is supported + +# Leaf 9H +# Intel DCA (Direct Cache Access) enumeration + + 9, 0, eax, 0, dca_enabled_in_bios , DCA is ena= bled in BIOS + +# Leaf AH +# Intel PMU (Performance Monitoring Unit) enumeration + + 0xa, 0, eax, 7:0, pmu_version , Performanc= e monitoring unit version ID + 0xa, 0, eax, 15:8, pmu_n_gcounters , Number of = general PMU counters per logical CPU + 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth o= f PMU general counters + 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of = cpuid leaf 0xa EBX bit vector + 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle= event not available + 0xa, 0, ebx, 1, no_insn_retired_evt , Instructio= n retired event not available + 0xa, 0, ebx, 2, no_refcycle_evt , Reference = cycles event not available + 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-refere= nce event not available + 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses= event not available + 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch ins= truction retired event not available + 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch mis= predict retired event not available + 0xa, 0, ebx, 7, no_td_slots_evt , Topdown sl= ots event not available + 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-func= tion PMU counters support bitmap + 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of = fixed PMU counters + 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth o= f PMU fixed counters + 0xa, 0, edx, 15, anythread_depr , AnyThread = deprecation + +# Leaf BH +# CPUs v1 extended topology enumeration + + 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width = of this level (previous levels inclusive) + 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CP= Us count across all instances of this domain + 0xb, 1:0, ecx, 7:0, domain_nr , This domai= n level (subleaf ID) + 0xb, 1:0, ecx, 15:8, domain_type , This domai= n type + 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID = of current logical CPU + +# Leaf DH +# Processor extended state enumeration + + 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (= bit 0) supported + 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (= bit 1) supported + 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (= bit 2) supported + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDRE= GS (bit 3) supported (MPX BND0-BND3 regs) + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCS= R (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMAS= K (bit 5) supported (AVX-512 k0-k7 regs) + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_H= i256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_= ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU = (bit 9) supported (XSAVE PKRU reg) + 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0.C= ET_U (bit 11) supported (CET supervisor state) + 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0.C= ET_S (bit 12) support (CET user state) + 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILEC= ONFIG (bit 17) supported (AMX can manage TILECONFIG) + 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILED= ATA (bit 18) supported (AMX can manage TILEDATA) + 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XRST= R area byte size, for XCR0 enabled features + 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRST= R area max byte size, all CPU features + 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.L= WP (bit 62) supported (Light-weight Profiling) + 0xd, 1, eax, 0, xsaveopt , XSAVEOPT i= nstruction + 0xd, 1, eax, 1, xsavec , XSAVEC ins= truction + 0xd, 1, eax, 2, xgetbv1 , XGETBV ins= truction with ECX =3D 1 + 0xd, 1, eax, 3, xsaves , XSAVES/XRS= TORS instructions (and XSS MSR) + 0xd, 1, eax, 4, xfd , Extended f= eature disable support + 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE a= rea size, all XCR0 and XMMS features enabled + 0xd, 1, ecx, 8, xss_pt , PT state, = supported + 0xd, 1, ecx, 10, xss_pasid , PASID stat= e, supported + 0xd, 1, ecx, 11, xss_cet_u , CET user s= tate, supported + 0xd, 1, ecx, 12, xss_cet_p , CET superv= isor state, supported + 0xd, 1, ecx, 13, xss_hdc , HDC state,= supported + 0xd, 1, ecx, 14, xss_uintr , UINTR stat= e, supported + 0xd, 1, ecx, 15, xss_lbr , LBR state,= supported + 0xd, 1, ecx, 16, xss_hwp , HWP state,= supported + 0xd, 63:2, eax, 31:0, xsave_sz , Size of sa= ve area for subleaf-N feature, in bytes + 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of = save area for subleaf-N feature, in bytes + 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N = describes an XSS bit, otherwise XCR0 bit + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, Whe= n compacted, subleaf-N feature xsave area is 64-byte aligned + +# Leaf FH +# Intel RDT / AMD PQoS resource monitoring + + 0xf, 0, ebx, 31:0, core_rmid_max , RMID max, = within this core, all types (0-based) + 0xf, 0, edx, 1, cqm_llc , LLC QoS-mo= nitoring supported + 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-mon= itoring counter bitwidth (24-based) + 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR= bit 61 is an overflow bit + 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR= conversion factor to bytes + 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-mon= itoring max RMID + 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occ= upancy monitoring supported + 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS tot= al bandwidth monitoring supported + 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS loc= al bandwidth monitoring supported =20 # Leaf 10H -# Intel RDT Allocation - - 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported - 0x10, 0, EBX, 2, l2c_rdt_alloc, L2 Cache Allocation supported - 0x10, 0, EBX, 3, mem_bw_alloc, Memory Bandwidth Allocation su= pported - +# Intel RDT / AMD PQoS allocation enumeration + + 0x10, 0, ebx, 1, cat_l3 , L3 Cache A= llocation Technology supported + 0x10, 0, ebx, 2, cat_l2 , L2 Cache A= llocation Technology supported + 0x10, 0, ebx, 3, mba , Memory Ban= dwidth Allocation supported + 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT = capacity bitmask length, minus-one notation + 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT = bitmap of allocation units + 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT C= OS updates should be infrequent + 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT = CDP (Code and Data Prioritization) + 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT = non-contiguous 1s value supported + 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT = max COS (Class of Service) supported + 0x10, 3, eax, 11:0, mba_max_delay , Max MBA th= rottling value; minus-one notation + 0x10, 3, ecx, 0, per_thread_mba , Per-thread= MBA controls are supported + 0x10, 3, ecx, 2, mba_delay_linear , Delay valu= es are linear + 0x10, 3, edx, 15:0, mba_cos_max , MBA max Cl= ass of Service supported =20 # Leaf 12H -# SGX Capability -# -# Some detailed SGX features not added yet - - 0x12, 0, EAX, 0, sgx1, L3 Cache Allocation supported - 0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported - +# Intel Software Guard Extensions (SGX) enumeration + + 0x12, 0, eax, 0, sgx1 , SGX1 leaf = functions supported + 0x12, 0, eax, 1, sgx2 , SGX2 leaf = functions supported + 0x12, 0, eax, 5, enclv_leaves , ENCLV leav= es (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported + 0x12, 0, eax, 6, encls_leaves , ENCLS leav= es (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported + 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf= EVERIFYREPORT2 supported + 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf= EUPDATESVN supported + 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf= EDECCSSA supported + 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC f= rame: reporting #PF and #GP exceptions inside enclave supported + 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC f= rame: reporting #CP exceptions inside enclave supported + 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum en= clave size in non-64-bit mode (log2) + 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum en= clave size in 64-bit mode (log2) + 0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES= .INIT supported (enclave initialized by EINIT) + 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES= .DEBUG supported (enclave permits debugger read/write) + 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES= .MODE64BIT supported (enclave runs in 64-bit mode) + 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES= .PROVISIONKEY supported (provisioning key available) + 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTE= S.EINITTOKEN_KEY supported (EINIT token key available) + 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES= .CET supported (enable CET attributes) + 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES= .KSS supported (Key Separation and Sharing enabled) + 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES= .AEXNOTIFY supported (enclave threads may get AEX notifications + 0x12, 1, ecx, 0, xfrm_x87 , Enclave XF= RM.X87 (bit 0) supported + 0x12, 1, ecx, 1, xfrm_sse , Enclave XF= RM.SEE (bit 1) supported + 0x12, 1, ecx, 2, xfrm_avx , Enclave XF= RM.AVX (bit 2) supported + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XF= RM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XF= RM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XF= RM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XF= RM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XF= RM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave XF= RM.PKRU (bit 9) supported (XSAVE PKRU reg) + 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XF= RM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) + 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XF= RM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) + 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf ty= pe (dictates output layout) + 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sectio= n base addr, bits[12:31] + 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sectio= n base addr, bits[32:51] + 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC sectio= n type / property encoding + 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC sectio= n size, bits[12:31] + 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC sectio= n size, bits[32:51] =20 # Leaf 14H -# Intel Processor Tracer -# +# Intel Processor Trace enumeration + + 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpuid = 0x14 subleaf + 0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_= CR3_MATCH is accessible + 0x14, 0, ebx, 1, psb_cyc , Configurab= le PSB and cycle-accurate mode + 0x14, 0, ebx, 2, ip_filtering , IP/TraceSt= op filtering; Warm-reset PT MSRs preservation + 0x14, 0, ebx, 3, mtc_timing , MTC timing= packet; COFI-based packets suppression + 0x14, 0, ebx, 4, ptwrite , PTWRITE su= pport + 0x14, 0, ebx, 5, power_event_trace , Power Even= t Trace support + 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PM= I preservation support + 0x14, 0, ebx, 7, event_trace , Event Trac= e packet generation through IA32_RTIT_CTL.EventEn + 0x14, 0, ebx, 8, tnt_disable , TNT packet= generation disable through IA32_RTIT_CTL.DisTNT + 0x14, 0, ecx, 0, topa_output , ToPA outpu= t scheme support + 0x14, 0, ecx, 1, topa_multiple_entries , ToPA table= s can hold multiple entries + 0x14, 0, ecx, 2, single_range_output , Single-ran= ge output scheme supported + 0x14, 0, ecx, 3, trance_transport_output, Trace Tran= sport subsystem output support + 0x14, 0, ecx, 31, ip_payloads_lip , IP payload= s have LIP values (CS base included) + 0x14, 1, eax, 2:0, num_address_ranges , Filtering = number of configurable Address Ranges + 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of = supported MTC period encodings + 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of = supported Cycle Threshold encodings + 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of = supported Configurable PSB frequency encodings =20 # Leaf 15H -# Time Stamp Counter and Nominal Core Crystal Clock Information +# Intel TSC (Time Stamp Counter) enumeration =20 - 0x15, 0, EAX, 31:0, tsc_denominator, The denominator of the TSC/= =E2=80=9Dcore crystal clock=E2=80=9D ratio - 0x15, 0, EBX, 31:0, tsc_numerator, The numerator of the TSC/=E2= =80=9Dcore crystal clock=E2=80=9D ratio - 0x15, 0, ECX, 31:0, nom_freq, Nominal frequency of the core crys= tal clock in Hz + 0x15, 0, eax, 31:0, tsc_denominator , Denominato= r of the TSC/'core crystal clock' ratio + 0x15, 0, ebx, 31:0, tsc_numerator , Numerator = of the TSC/'core crystal clock' ratio + 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core cryst= al clock nominal frequency, in Hz =20 # Leaf 16H -# Processor Frequency Information +# Intel processor fequency enumeration =20 - 0x16, 0, EAX, 15:0, cpu_base_freq, Processor Base Frequency in M= Hz - 0x16, 0, EBX, 15:0, cpu_max_freq, Maximum Frequency in MHz - 0x16, 0, ECX, 15:0, bus_freq, Bus (Reference) Frequency in MHz + 0x16, 0, eax, 15:0, cpu_base_mhz , Processor = base frequency, in MHz + 0x16, 0, ebx, 15:0, cpu_max_mhz , Processor = max frequency, in MHz + 0x16, 0, ecx, 15:0, bus_mhz , Bus refere= nce frequency, in MHz =20 # Leaf 17H -# System-On-Chip Vendor Attribute - - 0x17, 0, EAX, 31:0, max_socid, Maximum input value of supported = sub-leaf - 0x17, 0, EBX, 15:0, soc_vid, SOC Vendor ID - 0x17, 0, EBX, 16, std_vid, SOC Vendor ID is assigned via an in= dustry standard scheme - 0x17, 0, ECX, 31:0, soc_pid, SOC Project ID assigned by vendor - 0x17, 0, EDX, 31:0, soc_sid, SOC Stepping ID +# Intel SoC vendor attributes enumeration + + 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpuid = leaf 0x17 subleaf + 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor= ID + 0x17, 0, ebx, 16, is_vendor_scheme , Assigned b= y industry enumaeratoion scheme (not Intel) + 0x17, 0, ecx, 31:0, soc_proj_id , SoC projec= t ID, assigned by vendor + 0x17, 0, edx, 31:0, soc_stepping_id , Soc projec= t stepping ID, assigned by vendor + 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Bra= nd ID string, bytes subleaf_nr * (0 -> 3) + 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Bra= nd ID string, bytes subleaf_nr * (4 -> 7) + 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Bra= nd ID string, bytes subleaf_nr * (8 -> 11) + 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Bra= nd ID string, bytes subleaf_nr * (12 -> 15) =20 # Leaf 18H -# Deterministic Address Translation Parameters - +# Intel determenestic address translation (TLB) parameters + + 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpuid = 0x18 subleaf + 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-pa= ge entries supported + 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-pa= ge entries supported + 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-pa= ge entries supported + 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-pa= ge entries supported + 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/Soft= ) partitioning between logical CPUs sharing this struct + 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of as= sociativity + 0x18, 31:0, ecx, 31:0, n_sets , Number of = sets + 0x18, 31:0, edx, 4:0, tlb_type , Translatio= n cache type (TLB type) + 0x18, 31:0, edx, 7:5, tlb_cache_level , Translatio= n cache level (1-based) + 0x18, 31:0, edx, 8, is_fully_associative , Fully-asso= ciative structure + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num of= addressible IDs for logical CPUs sharing this TLB - 1 =20 # Leaf 19H -# Key Locker Leaf +# Intel Key Locker enumeration =20 + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only = key Locker restriction supported + 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt= key locker restriction supported + 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt= key locker restriction supported + 0x19, 0, ebx, 0, aes_keylocker , AES key lo= cker instructions supported + 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide k= ey locker instructions supported + 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker= MSRs and IWKEY backups supported + 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY = NoBackup parameter supported + 0x19, 0, ecx, 1, iwkey_rand , IWKEY rand= omization (KeySource encoding 1) supported =20 # Leaf 1AH -# Hybrid Information - - 0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core - +# Intel hybrid CPUs identification (e.g. Atom, Core) + + 0x1a, 0, eax, 23:0, core_native_model , This core'= s native model ID + 0x1a, 0, eax, 31:24, core_type , This core'= s type + +# Leaf 1BH +# Intel PCONFIG (Platform configuration) enumeration + + 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b= subleaf type + 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supporte= d PCONFIG target ID + 0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A supporte= d PCONFIG target ID + 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supporte= d PCONFIG target ID + +# Leaf 1CH +# Intel LBR (Last Branch Record) enumeration + + 0x1c, 0, eax, 0, lbr_depth_8 , Max stack = depth (number of LBR entries) =3D 8 + 0x1c, 0, eax, 1, lbr_depth_16 , Max stack = depth (number of LBR entries) =3D 16 + 0x1c, 0, eax, 2, lbr_depth_24 , Max stack = depth (number of LBR entries) =3D 24 + 0x1c, 0, eax, 3, lbr_depth_32 , Max stack = depth (number of LBR entries) =3D 32 + 0x1c, 0, eax, 4, lbr_depth_40 , Max stack = depth (number of LBR entries) =3D 40 + 0x1c, 0, eax, 5, lbr_depth_48 , Max stack = depth (number of LBR entries) =3D 48 + 0x1c, 0, eax, 6, lbr_depth_56 , Max stack = depth (number of LBR entries) =3D 56 + 0x1c, 0, eax, 7, lbr_depth_64 , Max stack = depth (number of LBR entries) =3D 64 + 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe= cleared on MWAIT C-state > C1 + 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP con= tain Last IP, otherwise effective IP + 0x1c, 0, ebx, 0, lbr_cpl , CPL filter= ing (non-zero IA32_LBR_CTL[2:1]) supported + 0x1c, 0, ebx, 1, lbr_branch_filter , Branch fil= tering (non-zero IA32_LBR_CTL[22:16]) supported + 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack= mode (IA32_LBR_CTL[3] =3D 1) supported + 0x1c, 0, ecx, 0, lbr_mispredict , Branch mis= prediction bit supported (IA32_LBR_x_INFO[63]) + 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs= (CPU cycles since last LBR entry) supported + 0x1c, 0, ecx, 2, lbr_branch_type , Branch typ= e field (IA32_LBR_INFO_x[59:56]) supported + 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-ev= ents logging support; bitmap for first 4 GP (general-purpose) Counters + +# Leaf 1DH +# Intel AMX (Advanced Matrix Extensions) tile information + + 0x1d, 0, eax, 31:0, amx_max_palette , Highest pa= lette ID / subleaf ID + 0x1d, 1, eax, 15:0, amx_palette_size , AMX palett= e total tiles size, in bytes + 0x1d, 1, eax, 31:16, amx_tile_size , AMX single= tile's size, in bytes + 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile s= ingle row's size, in bytes + 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palett= e number of tiles + 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile m= ax number of rows + +# Leaf 1EH +# Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration + + 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit = maximum height, K (rows or columns) + 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit = maxiumum SIMD dimension, N (column bytes) =20 # Leaf 1FH -# V2 Extended Topology - A preferred superset to leaf 0BH - - -# According to SDM -# 40000000H - 4FFFFFFFH is invalid range +# Intel extended topology enumeration v2 + + 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width = of this level (previous levels inclusive) + 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CP= Us count across all instances of this domain + 0x1f, 5:0, ecx, 7:0, domain_level , This domai= n level (subleaf ID) + 0x1f, 5:0, ecx, 15:8, domain_type , This domai= n type + 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID = of current logical CPU + +# Leaf 20H +# Intel HRESET (History Reset) enumeration + + 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20= max subleaf + 1 + 0x20, 0, ebx, 0, hreset_thread_director , HRESET of = Intel thread director is supported + +# Leaf 21H +# Intel TD (Trust Domain) guest execution environment enumeration + + 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor= ID string bytes 0 - 3 + 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor= ID string bytes 8 - 11 + 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor= ID string bytes 4 - 7 + +# Leaf 23H +# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) + + 0x23, 0, eax, 1, subleaf_1_counters , Subleaf 1,= PMU counters bitmaps, is valid + 0x23, 0, eax, 3, subleaf_3_events , Subleaf 3,= PMU events bitmaps, is valid + 0x23, 0, ebx, 0, unitmask2 , IA32_PERFE= VTSELx MSRs UnitMask2 is supported + 0x23, 0, ebx, 1, zbit , IA32_PERFE= VTSELx MSRs Z-bit is supported + 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-pu= rpose PMU counters bitmap + 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PMU = counters bitmap + 0x23, 3, eax, 0, core_cycles_evt , Core cycle= s event supported + 0x23, 3, eax, 1, insn_retired_evt , Instructio= ns retired event supported + 0x23, 3, eax, 2, ref_cycles_evt , Reference = cycles event supported + 0x23, 3, eax, 3, llc_refs_evt , Last-level= cache references event supported + 0x23, 3, eax, 4, llc_misses_evt , Last-level= cache misses event supported + 0x23, 3, eax, 5, br_insn_ret_evt , Branch ins= truction retired event supported + 0x23, 3, eax, 6, br_mispr_evt , Branch mis= predict retired event supported + 0x23, 3, eax, 7, td_slots_evt , Topdown sl= ots event supported + 0x23, 3, eax, 8, td_backend_bound_evt , Topdown ba= ckend bound event supported + 0x23, 3, eax, 9, td_bad_spec_evt , Topdown ba= d speculation event supported + 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown fr= ontend bound event supported + 0x23, 3, eax, 11, td_retiring_evt , Topdown re= tiring event support + +# Leaf 40000000H +# Maximum hypervisor standard leaf + hypervisor vendor string + +0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hy= pervisor standard leaf number +0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor= ID string bytes 0 - 3 +0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor= ID string bytes 4 - 7 +0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor= ID string bytes 8 - 11 + +# Leaf 80000000H +# Maximum extended leaf number + CPU vendor string (AMD) + +0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum ex= tended cpuid leaf supported +0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID = string bytes 0 - 3 +0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID = string bytes 8 - 11 +0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID = string bytes 4 - 7 =20 # Leaf 80000001H -# Extended Processor Signature and Feature Bits - -0x80000001, 0, EAX, 27:20, extfamily, Extended family -0x80000001, 0, EAX, 19:16, extmodel, Extended model -0x80000001, 0, EAX, 11:8, basefamily, Description of Family -0x80000001, 0, EAX, 11:8, basemodel, Model numbers vary with product -0x80000001, 0, EAX, 3:0, stepping, Processor stepping (revision) for = a specific model - -0x80000001, 0, EBX, 31:28, pkgtype, Specifies the package type - -0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode -0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mode -0x80000001, 0, ECX, 2, svm, Indicates support for: VMRUN, VMLOAD, V= MSAVE, CLGI, VMMCALL, and INVLPGA -0x80000001, 0, ECX, 3, extapicspace, Extended APIC register space -0x80000001, 0, ECX, 4, altmovecr8, Indicates support for LOCK MOV C= R0 means MOV CR8 -0x80000001, 0, ECX, 5, lzcnt, LZCNT -0x80000001, 0, ECX, 6, sse4a, EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD = instruction support -0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode -0x80000001, 0, ECX, 8, prefetchw, PREFETCHW -0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support -0x80000001, 0, ECX, 10, ibs, Instruction Based Sampling -0x80000001, 0, ECX, 11, xop, Extended operation support -0x80000001, 0, ECX, 12, skinit, SKINIT and STGI support -0x80000001, 0, ECX, 13, wdt, Watchdog timer support -0x80000001, 0, ECX, 15, lwp, Lightweight profiling support -0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support -0x80000001, 0, ECX, 17, tce, Translation cache extension -0x80000001, 0, ECX, 22, TopologyExtensions, Indicates support for Co= re::X86::Cpuid::CachePropEax0 and Core::X86::Cpuid::ExtApicId -0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core::= X86::Msr::PERF_CTL0 - 5 and Core::X86::Msr::PERF_CTR -0x80000001, 0, ECX, 24, perfctrextdf, Indicates support for Core::X8= 6::Msr::DF_PERF_CTL and Core::X86::Msr::DF_PERF_CTR -0x80000001, 0, ECX, 26, databreakpointextension, Indicates data brea= kpoint support for Core::X86::Msr::DR0_ADDR_MASK, Core::X86::Msr::DR1_ADDR_MA= SK, Core::X86::Msr::DR2_ADDR_MASK and Core::X86::Msr::DR3_ADDR_MASK -0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter supp= orted -0x80000001, 0, ECX, 28, perfctrextllc, Indicates support for L3 perf= ormance counter extensions -0x80000001, 0, ECX, 29, mwaitextended, MWAITX and MONITORX capabilit= y is supported -0x80000001, 0, ECX, 30, admskextn, Indicates support for address mas= k extension (to 32 bits and to all 4 DRs) for instruction breakpoints - -0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip -0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements -0x80000001, 0, EDX, 2, de, Debugging extensions, IO breakpoints, CR= 4.DE -0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages) -0x80000001, 0, EDX, 4, tsc, Time stamp counter, RDTSC/RDTSCP instru= ctions, CR4.TSD -0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with R= DMSR and WRMSR instructions -0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE) -0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE -0x80000001, 0, EDX, 8, cmpxchg8b, CMPXCHG8B instruction -0x80000001, 0, EDX, 9, apic, advanced programmable interrupt contro= ller (APIC) exists and is enabled -0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported -0x80000001, 0, EDX, 12, mtrr, Memory-type range registers -0x80000001, 0, EDX, 13, pge, Page global extension, CR4.PGE -0x80000001, 0, EDX, 14, mca, Machine check architecture, MCG_CAP -0x80000001, 0, EDX, 15, cmov, Conditional move instructions, CMOV, F= COMI, FCMOV -0x80000001, 0, EDX, 16, pat, Page attribute table -0x80000001, 0, EDX, 17, pse36, Page-size extensions -0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available -0x80000001, 0, EDX, 22, mmxext, AMD extensions to MMX instructions -0x80000001, 0, EDX, 23, mmx, MMX instructions -0x80000001, 0, EDX, 24, fxsr, FXSAVE and FXRSTOR instructions -0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction optimi= zations -0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported -0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available -0x80000001, 0, EDX, 29, lm, 64b Architecture supported -0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! instr= uctions -0x80000001, 0, EDX, 31, threednow, 3DNow! instructions - -# Leaf 80000002H/80000003H/80000004H -# Processor Brand String +# Extended CPU feature identifiers + +0x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID +0x80000001, 0, eax, 7:4, e_base_model , Base proce= ssor model +0x80000001, 0, eax, 11:8, e_base_family , Base proce= ssor family +0x80000001, 0, eax, 19:16, e_ext_model , Extended p= rocessor model +0x80000001, 0, eax, 27:20, e_ext_family , Extended p= rocessor family +0x80000001, 0, ebx, 15:0, brand_id , Brand ID +0x80000001, 0, ebx, 31:28, pkg_type , Package ty= pe +0x80000001, 0, ecx, 0, lahf_lm , LAHF and S= AHF in 64-bit mode +0x80000001, 0, ecx, 1, cmp_legacy , Multi-proc= essing legacy mode (No HT) +0x80000001, 0, ecx, 2, svm , Secure Vir= tual Machine +0x80000001, 0, ecx, 3, extapic , Extended A= PIC space +0x80000001, 0, ecx, 4, cr8_legacy , LOCK MOV C= R0 means MOV CR8 +0x80000001, 0, ecx, 5, abm , LZCNT adva= nced bit manipulation +0x80000001, 0, ecx, 6, sse4a , SSE4A supp= ort +0x80000001, 0, ecx, 7, misalignsse , Misaligned= SSE mode +0x80000001, 0, ecx, 8, 3dnowprefetch , 3DNow PREF= ETCH/PREFETCHW support +0x80000001, 0, ecx, 9, osvw , OS visible= workaround +0x80000001, 0, ecx, 10, ibs , Instructio= n based sampling +0x80000001, 0, ecx, 11, xop , XOP: exten= ded operation (AVX instructions) +0x80000001, 0, ecx, 12, skinit , SKINIT/STG= I support +0x80000001, 0, ecx, 13, wdt , Watchdog t= imer support +0x80000001, 0, ecx, 15, lwp , Lightweigh= t profiling +0x80000001, 0, ecx, 16, fma4 , 4-operand = FMA instruction +0x80000001, 0, ecx, 17, tce , Translatio= n cache extension +0x80000001, 0, ecx, 19, nodeid_msr , NodeId MSR= (0xc001100c) +0x80000001, 0, ecx, 21, tbm , Trailing b= it manipulations +0x80000001, 0, ecx, 22, topoext , Topology E= xtensions (cpuid leaf 0x8000001d) +0x80000001, 0, ecx, 23, perfctr_core , Core perfo= rmance counter extensions +0x80000001, 0, ecx, 24, perfctr_nb , NB/DF perf= ormance counter extensions +0x80000001, 0, ecx, 26, bpext , Data acces= s breakpoint extension +0x80000001, 0, ecx, 27, ptsc , Performanc= e time-stamp counter +0x80000001, 0, ecx, 28, perfctr_llc , LLC (L3) p= erformance counter extensions +0x80000001, 0, ecx, 29, mwaitx , MWAITX/MON= ITORX support +0x80000001, 0, ecx, 30, addr_mask_ext , Breakpoint= address mask extension (to bit 31) +0x80000001, 0, edx, 0, e_fpu , Floating-P= oint Unit on-chip (x87) +0x80000001, 0, edx, 1, e_vme , Virtual-80= 86 Mode Extensions +0x80000001, 0, edx, 2, e_de , Debugging = Extensions +0x80000001, 0, edx, 3, e_pse , Page Size = Extension +0x80000001, 0, edx, 4, e_tsc , Time Stamp= Counter +0x80000001, 0, edx, 5, e_msr , Model-Spec= ific Registers (RDMSR and WRMSR support) +0x80000001, 0, edx, 6, pae , Physical A= ddress Extensions +0x80000001, 0, edx, 7, mce , Machine Ch= eck Exception +0x80000001, 0, edx, 8, cx8 , CMPXCHG8B = instruction +0x80000001, 0, edx, 9, apic , APIC on-ch= ip +0x80000001, 0, edx, 11, syscall , SYSCALL an= d SYSRET instructions +0x80000001, 0, edx, 12, mtrr , Memory Typ= e Range Registers +0x80000001, 0, edx, 13, pge , Page Globa= l Extensions +0x80000001, 0, edx, 14, mca , Machine Ch= eck Architecture +0x80000001, 0, edx, 15, cmov , Conditiona= l Move Instruction +0x80000001, 0, edx, 16, pat , Page Attri= bute Table +0x80000001, 0, edx, 17, pse36 , Page Size = Extension (36-bit) +0x80000001, 0, edx, 19, mp , Out-of-spe= c AMD Multiprocessing bit +0x80000001, 0, edx, 20, nx , No-execute= page protection +0x80000001, 0, edx, 22, mmxext , AMD MMX ex= tensions +0x80000001, 0, edx, 24, e_fxsr , FXSAVE and= FXRSTOR instructions +0x80000001, 0, edx, 25, fxsr_opt , FXSAVE and= FXRSTOR optimizations +0x80000001, 0, edx, 26, pdpe1gb , 1-GB large= page support +0x80000001, 0, edx, 27, rdtscp , RDTSCP ins= truction +0x80000001, 0, edx, 29, lm , Long mode = (x86-64, 64-bit support) +0x80000001, 0, edx, 30, 3dnowext , AMD 3DNow = extensions +0x80000001, 0, edx, 31, 3dnow , 3DNow inst= ructions + +# Leaf 80000002H +# CPU brand ID string, bytes 0 - 15 + +0x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand = ID string, bytes 0 - 3 +0x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand = ID string, bytes 4 - 7 +0x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand = ID string, bytes 8 - 11 +0x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand = ID string, bytes 12 - 15 + +# Leaf 80000003H +# CPU brand ID string, bytes 16 - 31 + +0x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand = ID string bytes, 16 - 19 +0x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand = ID string bytes, 20 - 23 +0x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand = ID string bytes, 24 - 27 +0x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand = ID string bytes, 28 - 31 + +# Leaf 80000004H +# CPU brand ID string, bytes 32 - 47 + +0x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand = ID string, bytes 32 - 35 +0x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand = ID string, bytes 36 - 39 +0x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand = ID string, bytes 40 - 43 +0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand = ID string, bytes 44 - 47 =20 # Leaf 80000005H -# Reserved +# AMD L1 cache and L1 TLB enumeration + +0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #e= ntires, 2M and 4M pages +0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB as= sociativity, 2M and 4M pages +0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB #e= ntires, 2M and 4M pages +0x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB as= sociativity, 2M and 4M pages +0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #e= ntries, 4K pages +0x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB as= sociativity, 4K pages +0x80000005, 0, ebx, 23:16, l1_dtlb_4k_nentries , L1 DTLB #e= ntries, 4K pages +0x80000005, 0, ebx, 31:24, l1_dtlb_4k_assoc , L1 DTLB as= sociativity, 4K pages +0x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache = line size, in bytes +0x80000005, 0, ecx, 15:8, l1_dcache_nlines , L1 dcache = lines per tag +0x80000005, 0, ecx, 23:16, l1_dcache_assoc , L1 dcache = associativity +0x80000005, 0, ecx, 31:24, l1_dcache_size_kb , L1 dcache = size, in KB +0x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache = line size, in bytes +0x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icache = lines per tag +0x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icache = associativity +0x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache = size, in KB =20 # Leaf 80000006H -# Extended L2 Cache Features - -0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes -0x80000006, 0, ECX, 15:12, l2c_assoc, L2 Associativity -0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units - +# (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration + +0x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB #e= ntries, 2M and 4M pages +0x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB as= sociativity, 2M and 4M pages +0x80000006, 0, eax, 27:16, l2_dtlb_2m_4m_nentries , L2 dTLB #e= ntries, 2M and 4M pages +0x80000006, 0, eax, 31:28, l2_dtlb_2m_4m_assoc , L2 dTLB as= sociativity, 2M and 4M pages +0x80000006, 0, ebx, 11:0, l2_itlb_4k_nentries , L2 iTLB #e= ntries, 4K pages +0x80000006, 0, ebx, 15:12, l2_itlb_4k_assoc , L2 iTLB as= sociativity, 4K pages +0x80000006, 0, ebx, 27:16, l2_dtlb_4k_nentries , L2 dTLB #e= ntries, 4K pages +0x80000006, 0, ebx, 31:28, l2_dtlb_4k_assoc , L2 dTLB as= sociativity, 4K pages +0x80000006, 0, ecx, 7:0, l2_line_size , L2 cache l= ine size, in bytes +0x80000006, 0, ecx, 11:8, l2_nlines , L2 cache n= umber of lines per tag +0x80000006, 0, ecx, 15:12, l2_assoc , L2 cache a= ssociativity +0x80000006, 0, ecx, 31:16, l2_size_kb , L2 cache s= ize, in KB +0x80000006, 0, edx, 7:0, l3_line_size , L3 cache l= ine size, in bytes +0x80000006, 0, edx, 11:8, l3_nlines , L3 cache n= umber of lines per tag +0x80000006, 0, edx, 15:12, l3_assoc , L3 cache a= ssociativity +0x80000006, 0, edx, 31:18, l3_size_range , L3 cache s= ize range =20 # Leaf 80000007H - -0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available - +# CPU power management (mostly AMD) and AMD RAS enumeration + +0x80000007, 0, ebx, 0, overflow_recov , MCA overfl= ow conditions not fatal +0x80000007, 0, ebx, 1, succor , Software c= ontainment of UnCORRectable errors +0x80000007, 0, ebx, 2, hw_assert , Hardware a= ssert MSRs +0x80000007, 0, ebx, 3, smca , Scalable M= CA (MCAX MSRs) +0x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU power = sample time ratio +0x80000007, 0, edx, 0, digital_temp , Digital te= mprature sensor +0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! = frequency scaling +0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW! = voltage scaling +0x80000007, 0, edx, 3, thermal_trip , THERMTRIP = (Thermal Trip) +0x80000007, 0, edx, 4, hw_thermal_control , Hardware t= hermal control +0x80000007, 0, edx, 5, sw_thermal_control , Software t= hermal control +0x80000007, 0, edx, 6, 100mhz_steps , 100 MHz mu= ltiplier control +0x80000007, 0, edx, 7, hw_pstate , Hardware P= -state control +0x80000007, 0, edx, 8, constant_tsc , TSC ticks = at constant rate across all P and C states +0x80000007, 0, edx, 9, cpb , Core perfo= rmance boost +0x80000007, 0, edx, 10, eff_freq_ro , Read-only = effective frequency interface +0x80000007, 0, edx, 11, proc_feedback , Processor = feedback interface (deprecated) +0x80000007, 0, edx, 12, acc_power , Processor = power reporting interface +0x80000007, 0, edx, 13, connected_standby , CPU Connec= ted Standby support +0x80000007, 0, edx, 14, rapl , Runtime Av= erage Power Limit interface =20 # Leaf 80000008H - -0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits -0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits -0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD - -# 0x8000001E -# EAX: Extended APIC ID -0x8000001E, 0, EAX, 31:0, extended_apic_id, Extended APIC ID -# EBX: Core Identifiers -0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID -0x8000001E, 0, EBX, 15:8, threads_per_core, The number of threads per core= is threads_per_core + 1 -# ECX: Node Identifiers -0x8000001E, 0, ECX, 7:0, node_id, Node ID -0x8000001E, 0, ECX, 10:8, nodes_per_processor, Nodes per processor { 0: 1 = node, else reserved } - -# 8000001F: AMD Secure Encryption -0x8000001F, 0, EAX, 0, sme, Secure Memory Encryption -0x8000001F, 0, EAX, 1, sev, Secure Encrypted Virtualization -0x8000001F, 0, EAX, 2, vmpgflush, VM Page Flush MSR -0x8000001F, 0, EAX, 3, seves, SEV Encrypted State -0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable memo= ry encryption -0x8000001F, 0, EBX, 11:6, mem_encrypt_physaddr_width, Reduction of physica= l address space in bits with SME enabled -0x8000001F, 0, ECX, 31:0, num_encrypted_guests, Maximum ASID value that ma= y be used for an SEV-enabled guest -0x8000001F, 0, EDX, 31:0, minimum_sev_asid, Minimum ASID value that must b= e used for an SEV-enabled, SEV-ES-disabled guest +# CPU capacity parameters and extended feature flags (mostly AMD) + +0x80000008, 0, eax, 7:0, phys_addr_bits , Max physic= al address bits +0x80000008, 0, eax, 15:8, virt_addr_bits , Max virtua= l address bits +0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested= -paging guest physical address bits +0x80000008, 0, ebx, 0, clzero , CLZERO sup= ported +0x80000008, 0, ebx, 1, irperf , Instructio= n retired counter MSR +0x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XRST= OR always saves/restores FPU error pointers +0x80000008, 0, ebx, 3, invlpgb , INVLPGB br= oadcasts a TLB invalidate to all threads +0x80000008, 0, ebx, 4, rdpru , RDPRU (Rea= d Processor Register at User level) supported +0x80000008, 0, ebx, 6, mba , Memory Ban= dwidth Allocation (AMD bit) +0x80000008, 0, ebx, 8, mcommit , MCOMMIT (M= emory commit) supported +0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD s= upported +0x80000008, 0, ebx, 12, amd_ibpb , Indirect B= ranch Prediction Barrier +0x80000008, 0, ebx, 13, wbinvd_int , Interrupti= ble WBINVD/WBNOINVD +0x80000008, 0, ebx, 14, amd_ibrs , Indirect B= ranch Restricted Speculation +0x80000008, 0, ebx, 15, amd_stibp , Single Thr= ead Indirect Branch Prediction mode +0x80000008, 0, ebx, 16, ibrs_always_on , IBRS alway= s-on preferred +0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP alwa= ys-on preferred +0x80000008, 0, ebx, 18, ibrs_fast , IBRS is pr= eferred over software solution +0x80000008, 0, ebx, 19, ibrs_same_mode , IBRS provi= des same mode protection +0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE= ] bit (Long-Mode Segment Limit Enable) unsupported +0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RA= X[5] bit can be set (nested translations) +0x80000008, 0, ebx, 23, amd_ppin , Protected = Processor Inventory Number +0x80000008, 0, ebx, 24, amd_ssbd , Speculativ= e Store Bypass Disable +0x80000008, 0, ebx, 25, virt_ssbd , virtualize= d SSBD (Speculative Store Bypass Disable) +0x80000008, 0, ebx, 26, amd_ssb_no , SSBD not n= eeded (fixed in HW) +0x80000008, 0, ebx, 27, cppc , Collaborat= ive Processor Performance Control +0x80000008, 0, ebx, 28, amd_psfd , Predictive= Store Forward Disable +0x80000008, 0, ebx, 29, btc_no , CPU not af= fected by Branch Type Confusion +0x80000008, 0, ebx, 30, ibpb_ret , IBPB clear= s RSB/RAS too +0x80000008, 0, ebx, 31, brs , Branch Sam= pling supported +0x80000008, 0, ecx, 7:0, cpu_nthreads , Number of = physical threads - 1 +0x80000008, 0, ecx, 15:12, apicid_coreid_len , Number of = thread core ID bits (shift) in APIC ID +0x80000008, 0, ecx, 17:16, perf_tsc_len , Performanc= e time-stamp counter size +0x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB ma= ximum page count +0x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max = register ID (ECX input) + +# Leaf 8000000AH +# AMD SVM (Secure Virtual Machine) enumeration + +0x8000000a, 0, eax, 7:0, svm_version , SVM revisi= on number +0x8000000a, 0, ebx, 31:0, svm_nasid , Number of = address space identifiers (ASID) +0x8000000a, 0, edx, 0, npt , Nested pag= ing +0x8000000a, 0, edx, 1, lbrv , LBR virtua= lization +0x8000000a, 0, edx, 2, svm_lock , SVM lock +0x8000000a, 0, edx, 3, nrip_save , NRIP save = support on #VMEXIT +0x8000000a, 0, edx, 4, tsc_scale , MSR based = TSC rate control +0x8000000a, 0, edx, 5, vmcb_clean , VMCB clean= bits support +0x8000000a, 0, edx, 6, flushbyasid , Flush by A= SID + Extended VMCB TLB_Control +0x8000000a, 0, edx, 7, decodeassists , Decode Ass= ists support +0x8000000a, 0, edx, 10, pausefilter , Pause inte= rcept filter +0x8000000a, 0, edx, 12, pfthreshold , Pause filt= er threshold +0x8000000a, 0, edx, 13, avic , Advanced v= irtual interrupt controller +0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual VM= SAVE/VMLOAD (nested virt) +0x8000000a, 0, edx, 16, vgif , Virtualize= the Global Interrupt Flag +0x8000000a, 0, edx, 17, gmet , Guest mode= execution trap +0x8000000a, 0, edx, 18, x2avic , Virtual x2= APIC +0x8000000a, 0, edx, 19, sss_check , Supervisor= Shadow Stack restrictions +0x8000000a, 0, edx, 20, v_spec_ctrl , Virtual SP= EC_CTRL +0x8000000a, 0, edx, 21, ro_gpt , Read-Only = guest page table support +0x8000000a, 0, edx, 23, h_mce_override , Host MCE o= verride +0x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC in= tercept + INVLPGB/TLBSYNC in VMCB +0x8000000a, 0, edx, 25, vnmi , NMI virtua= lization +0x8000000a, 0, edx, 26, ibs_virt , IBS Virtua= lization +0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended L= VT offset fault change +0x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME= addr check + +# Leaf 80000019H +# AMD TLB 1G-pages enumeration + +0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #e= ntries, 1G pages +0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB as= sociativity, 1G pages +0x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #e= ntries, 1G pages +0x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB as= sociativity, 1G pages +0x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #e= ntries, 1G pages +0x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB as= sociativity, 1G pages +0x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #e= ntries, 1G pages +0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB as= sociativity, 1G pages + +# Leaf 8000001AH +# AMD instruction optimizations enumeration + +0x8000001a, 0, eax, 0, fp_128 , Internal F= P/SIMD exec data path is 128-bits wide +0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU*= better than MOVL*/MOVH* +0x8000001a, 0, eax, 2, fp_256 , internal F= P/SSE exec data path is 256-bits wide + +# Leaf 8000001BH +# AMD IBS (Instruction-Based Sampling) enumeration + +0x8000001b, 0, eax, 0, ibs_flags_valid , IBS featur= e flags valid +0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch = sampling supported +0x8000001b, 0, eax, 2, ibs_op_sampling , IBS execut= ion sampling supported +0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/w= rite of op counter supported +0x8000001b, 0, eax, 4, ibs_op_count , IBS OP cou= nting mode supported +0x8000001b, 0, eax, 5, ibs_branch_target , IBS branch= target address reporting supported +0x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpC= urCnt/IbsOpMaxCnt extend by 7 bits +0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invali= d RIP indication supported +0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused = branch micro-op indication supported +0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch = Control Extended MSR (0xc001103c) supported +0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op dat= a 4 MSR supported +0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-mis= s filtering supported (Zen4+) + +# Leaf 8000001CH +# AMD LWP (Lightweight Profiling) + +0x8000001c, 0, eax, 0, os_lwp_avail , LWP is ava= ilable to application programs (supported by OS) +0x8000001c, 0, eax, 1, os_lpwval , LWPVAL ins= truction (EventId=3D1) is supported by OS +0x8000001c, 0, eax, 2, os_lwp_ire , Instructio= ns Retired Event (EventId=3D2) is supported by OS +0x8000001c, 0, eax, 3, os_lwp_bre , Branch Ret= ired Event (EventId=3D3) is supported by OS +0x8000001c, 0, eax, 4, os_lwp_dme , DCache Mis= s Event (EventId=3D4) is supported by OS +0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Clocks= Not Halted event (EventId=3D5) is supported by OS +0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refere= nce clocks Not Halted event (EventId=3D6) is supported by OS +0x8000001c, 0, eax, 29, os_lwp_cont , LWP sampli= ng in continuous mode is supported by OS +0x8000001c, 0, eax, 30, os_lwp_ptsc , Performanc= e Time Stamp Counter in event records is supported by OS +0x8000001c, 0, eax, 31, os_lwp_int , Interrupt = on threshold overflow is supported by OS +0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Contro= l Block size, in quadwords +0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP event = record size, in bytes +0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max su= pported EventId value (EventID 255 not included) +0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP events= area offset in the LWP Control Block +0x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of bit= s in cache latency counters (10 to 31) +0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache miss= events report the data address of the reference +0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount by = which cache latency is rounded +0x8000001c, 0, ecx, 15:9, lwp_version , LWP implem= entation version +0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event = ring buffer min size, in units of 32 event records +0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches R= etired events can be filtered +0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filteri= ng (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported +0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-rela= ted events can be filtered by cache level +0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-rela= ted events can be filtered by latency +0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is ava= ilable in Hardware +0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL ins= truction (EventId=3D1) is available in HW +0x8000001c, 0, edx, 2, hw_lwp_ire , Instructio= ns Retired Event (EventId=3D2) is available in HW +0x8000001c, 0, edx, 3, hw_lwp_bre , Branch Ret= ired Event (EventId=3D3) is available in HW +0x8000001c, 0, edx, 4, hw_lwp_dme , DCache Mis= s Event (EventId=3D4) is available in HW +0x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Clocks= Not Halted event (EventId=3D5) is available in HW +0x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Refere= nce clocks Not Halted event (EventId=3D6) is available in HW +0x8000001c, 0, edx, 29, hw_lwp_cont , LWP sampli= ng in continuous mode is available in HW +0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performanc= e Time Stamp Counter in event records is available in HW +0x8000001c, 0, edx, 31, hw_lwp_int , Interrupt = on threshold overflow is available in HW + +# Leaf 8000001DH +# AMD deterministic cache parameters + +0x8000001d, 31:0, eax, 4:0, cache_type , Cache type= field +0x8000001d, 31:0, eax, 7:5, cache_level , Cache leve= l (1-based) +0x8000001d, 31:0, eax, 8, cache_self_init , Self-initi= alizing cache level +0x8000001d, 31:0, eax, 9, fully_associative , Fully-asso= ciative cache +0x8000001d, 31:0, eax, 25:14, num_threads_sharing , Number of = logical CPUs sharing cache +0x8000001d, 31:0, ebx, 11:0, cache_linesize , System coh= erency line size (0-based) +0x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical l= ine partitions (0-based) +0x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of as= sociativity (0-based) +0x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache numb= er of sets (0-based) +0x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INV= D not guaranteed for Remote Lower-Level caches +0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is i= nclusive of Lower-Level caches + +# Leaf 8000001EH +# AMD CPU topology enumeration + +0x8000001e, 0, eax, 31:0, ext_apic_id , Extended A= PIC ID +0x8000001e, 0, ebx, 7:0, core_id , Unique per= -socket logical core unit ID +0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads p= er core (zero-based) +0x8000001e, 0, ecx, 7:0, node_id , Node (die)= ID of invoking logical CPU +0x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes in = invoking logical CPU's package/socket + +# Leaf 8000001FH +# AMD encrypted memory capabilities enumeration (SME/SEV) + +0x8000001f, 0, eax, 0, sme , Secure Mem= ory Encryption supported +0x8000001f, 0, eax, 1, sev , Secure Enc= rypted Virtualization supported +0x8000001f, 0, eax, 2, vm_page_flush , VM Page Fl= ush MSR (0xc001011e) available +0x8000001f, 0, eax, 3, sev_es , SEV Encryp= ted State supported +0x8000001f, 0, eax, 4, sev_nested_paging , SEV secure= nested paging supported +0x8000001f, 0, eax, 5, vm_permission_levels , VMPL suppo= rted +0x8000001f, 0, eax, 6, rpmquery , RPMQUERY i= nstruction supported +0x8000001f, 0, eax, 7, vmpl_sss , VMPL super= visor shadwo stack supported +0x8000001f, 0, eax, 8, secure_tsc , Secure TSC= supported +0x8000001f, 0, eax, 9, v_tsc_aux , Hardware v= irtualizes TSC_AUX +0x8000001f, 0, eax, 10, sme_coherent , HW enforce= s cache coherency across encryption domains +0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest = mandates 64-bit hypervisor +0x8000001f, 0, eax, 12, restricted_injection , Restricted= Injection supported +0x8000001f, 0, eax, 13, alternate_injection , Alternate = Injection supported +0x8000001f, 0, eax, 14, debug_swap , SEV-ES: fu= ll debug state swap is supported +0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Di= sallowing IBS use by the host is supported +0x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Tr= ansparent Encryption +0x8000001f, 0, eax, 17, vmgexit_paremeter , VmgexitPar= ameter is supported in SEV_FEATURES +0x8000001f, 0, eax, 18, virt_tom_msr , Virtual TO= M MSR is supported +0x8000001f, 0, eax, 19, virt_ibs , IBS state = virtualization is supported for SEV-ES guests +0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA regis= ter protection is supported +0x8000001f, 0, eax, 25, smt_protection , SMT protec= tion is supported +0x8000001f, 0, eax, 28, svsm_page_msr , SVSM commu= nication page MSR (0xc001f000h) is supported +0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUP= DATE/VIRT_PSMASH MSRs are supported +0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit nu= mber used to enable memory encryption +0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reductio= n of phys address space when encryption is enabled, in bits +0x8000001f, 0, ebx, 15:12, vmpl_count , Number of = VM permission levels (VMPL) supported +0x8000001f, 0, ecx, 31:0, enc_guests_max , Max suppor= ted number of simultaneous encrypted guests +0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum AS= ID for SEV-enabled SEV-ES-disabled guest + +# Leaf 80000020H +# AMD Platform QoS extended feature IDs + +0x80000020, 0, ebx, 1, mba , Memory Ban= dwidth Allocation support +0x80000020, 0, ebx, 2, smba , Slow Memor= y Bandwidth Allocation support +0x80000020, 0, ebx, 3, bmec , Bandwidth = Monitoring Event Configuration support +0x80000020, 0, ebx, 4, l3rr , L3 Range R= eservation support +0x80000020, 1, eax, 31:0, mba_limit_len , MBA enforc= ement limit size +0x80000020, 1, edx, 31:0, mba_cos_max , MBA max Cl= ass of Service number (zero-based) +0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enfor= cement limit size +0x80000020, 2, edx, 31:0, smba_cos_max , SMBA max C= lass of Service number (zero-based) +0x80000020, 3, ebx, 7:0, bmec_num_events , BMEC numbe= r of bandwidth events available +0x80000020, 3, ecx, 0, bmec_local_reads , Local NUMA= reads can be tracked +0x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUM= A reads can be tracked +0x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA= non-temporal writes can be tracked +0x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUM= A non-temporal writes can be tracked +0x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA= slow-memory reads can be tracked +0x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUM= A slow-memory reads can be tracked +0x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty QoS = victims to all types of memory can be tracked + +# Leaf 80000021H +# AMD extended features enumeration 2 + +0x80000021, 0, eax, 0, no_nested_data_bp , No nested = data breakpoints +0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {= FS,GS,KERNEL_GS}_BASE is non-serializing +0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE alw= ays serializing / synchronizes RDTSC +0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging= configuration lock is supported +0x80000021, 0, eax, 6, null_sel_clr_base , Null selec= tor clears base +0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR U= pper Address Ignore Enable bit supported +0x80000021, 0, eax, 8, autoibrs , EFER MSR A= utomatic IBRS enable bit supported +0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MS= R (0xc0010116) is not present +0x80000021, 0, eax, 10, fsrs_supported , Fast Short= Rep Stosb (FSRS) is supported +0x80000021, 0, eax, 11, fsrc_supported , Fast Short= Repe Cmpsb (FSRC) is supported +0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch c= ontrol MSR is supported +0x80000021, 0, eax, 17, user_cpuid_disable , #GP when e= xecuting CPUID at CPL > 0 is supported +0x80000021, 0, eax, 18, epsf_supported , Enhanced P= redictive Store Forwarding (EPSF) is supported +0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of mi= crocode patch, in 16-byte units + +# Leaf 80000022H +# AMD Performance Monitoring v2 enumeration + +0x80000022, 0, eax, 0, perfmon_v2 , Performanc= e monitoring v2 supported +0x80000022, 0, eax, 1, lbr_v2 , Last Branc= h Record v2 extensions (LBR Stack) +0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing c= ore performance counters / LBR Stack supported +0x80000022, 0, ebx, 3:0, n_pmc_core , Number of = core perfomance counters +0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of = available LBR stack entries +0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of = available northbridge (data fabric) performance counters +0x80000022, 0, ebx, 21:16, n_pmc_umc , Number of = available UMC performance counters +0x80000022, 0, ecx, 31:0, active_umc_bitmask , Active UMC= s bitmask + +# Leaf 80000023H +# AMD Secure Multi-key Encryption enumeration + +0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK en= cryption mode is supported +0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mo= de: total num of available encryption keys + +# Leaf 80000026H +# AMD extended topology enumeration v2 + +0x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit width = of this level (previous levels inclusive) +0x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This core = has a power efficiency ranking +0x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This domai= n level has hybrid (E, P) cores +0x80000026, 3:0, eax, 31, domain_core_count_asymm, The 'Core'= domain has asymmetric cores count +0x80000026, 3:0, ebx, 15:0, domain_lcpus_count , Number of = logical CPUs at this domain instance +0x80000026, 3:0, ebx, 23:16, core_pwreff_ranking , This core'= s static power efficiency ranking +0x80000026, 3:0, ebx, 27:24, core_native_model_id , This core'= s native model ID +0x80000026, 3:0, ebx, 31:28, core_type , This core'= s type +0x80000026, 3:0, ecx, 7:0, domain_level , This domai= n level (subleaf ID) +0x80000026, 3:0, ecx, 15:8, domain_type , This domai= n type +0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID = of current logical CPU diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 24b7d017ec2c..1b25c0a95d3f 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -7,7 +7,8 @@ #include #include =20 -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define min(a, b) (((a) < (b)) ? (a) : (b)) =20 typedef unsigned int u32; typedef unsigned long long u64; @@ -76,7 +77,6 @@ struct cpuid_range { */ struct cpuid_range *leafs_basic, *leafs_ext; =20 -static int num_leafs; static bool is_amd; static bool show_details; static bool show_raw; @@ -98,27 +98,17 @@ static inline void cpuid(u32 *eax, u32 *ebx, u32 *ecx, u3= 2 *edx) =20 static inline bool has_subleafs(u32 f) { - if (f =3D=3D 0x7 || f =3D=3D 0xd) - return true; - - if (is_amd) { - if (f =3D=3D 0x8000001d) + u32 with_subleaves[] =3D { + 0x4, 0x7, 0xb, 0xd, 0xf, 0x10, 0x12, + 0x14, 0x17, 0x18, 0x1b, 0x1d, 0x1f, 0x23, + 0x8000001d, 0x80000020, 0x80000026, + }; + + for (unsigned i =3D 0; i < ARRAY_SIZE(with_subleaves); i++) + if (f =3D=3D with_subleaves[i]) return true; - return false; - } =20 - switch (f) { - case 0x4: - case 0xb: - case 0xf: - case 0x10: - case 0x14: - case 0x18: - case 0x1f: - return true; - default: - return false; - } + return false; } =20 static void leaf_print_raw(struct subleaf *leaf) @@ -204,15 +194,12 @@ static void raw_dump_range(struct cpuid_range *range) } } =20 -#define MAX_SUBLEAF_NUM 32 +#define MAX_SUBLEAF_NUM 64 struct cpuid_range *setup_cpuid_range(u32 input_eax) { - u32 max_func, idx_func; - int subleaf; + u32 max_func, idx_func, subleaf, max_subleaf; + u32 eax, ebx, ecx, edx, f =3D input_eax; struct cpuid_range *range; - u32 eax, ebx, ecx, edx; - u32 f =3D input_eax; - int max_subleaf; bool allzero; =20 eax =3D input_eax; @@ -246,7 +233,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) allzero =3D cpuid_store(range, f, subleaf, eax, ebx, ecx, edx); if (allzero) continue; - num_leafs++; =20 if (!has_subleafs(f)) continue; @@ -257,11 +243,18 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) * Some can provide the exact number of subleafs, * others have to be tried (0xf) */ - if (f =3D=3D 0x7 || f =3D=3D 0x14 || f =3D=3D 0x17 || f =3D=3D 0x18) - max_subleaf =3D (eax & 0xff) + 1; - + if (f =3D=3D 0x7 || f =3D=3D 0x14 || f =3D=3D 0x17 || f =3D=3D 0x18 || f = =3D=3D 0x1d) + max_subleaf =3D min((eax & 0xff) + 1, max_subleaf); if (f =3D=3D 0xb) max_subleaf =3D 2; + if (f =3D=3D 0x1f) + max_subleaf =3D 6; + if (f =3D=3D 0x23) + max_subleaf =3D 4; + if (f =3D=3D 0x80000020) + max_subleaf =3D 4; + if (f =3D=3D 0x80000026) + max_subleaf =3D 5; =20 for (subleaf =3D 1; subleaf < max_subleaf; subleaf++) { eax =3D f; @@ -272,7 +265,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) eax, ebx, ecx, edx); if (allzero) continue; - num_leafs++; } =20 } @@ -313,6 +305,8 @@ static int parse_line(char *line) struct bits_desc *bdesc; int reg_index; char *start, *end; + u32 subleaf_start, subleaf_end; + unsigned bit_start, bit_end; =20 /* Skip comments and NULL line */ if (line[0] =3D=3D '#' || line[0] =3D=3D '\n') @@ -351,13 +345,25 @@ static int parse_line(char *line) return 0; =20 /* subleaf */ - sub =3D strtoul(tokens[1], NULL, 0); - if ((int)sub > func->nr) - return -1; + buf =3D tokens[1]; + end =3D strtok(buf, ":"); + start =3D strtok(NULL, ":"); + subleaf_end =3D strtoul(end, NULL, 0); + + /* A subleaf range is given? */ + if (start) { + subleaf_start =3D strtoul(start, NULL, 0); + subleaf_end =3D min(subleaf_end, (u32)(func->nr - 1)); + if (subleaf_start > subleaf_end) + return 0; + } else { + subleaf_start =3D subleaf_end; + if (subleaf_start > (u32)(func->nr - 1)) + return 0; + } =20 - leaf =3D &func->leafs[sub]; + /* register */ buf =3D tokens[2]; - if (strcasestr(buf, "EAX")) reg_index =3D R_EAX; else if (strcasestr(buf, "EBX")) @@ -369,23 +375,23 @@ static int parse_line(char *line) else goto err_exit; =20 - reg =3D &leaf->info[reg_index]; - bdesc =3D ®->descs[reg->nr++]; - /* bit flag or bits field */ buf =3D tokens[3]; - end =3D strtok(buf, ":"); - bdesc->end =3D strtoul(end, NULL, 0); - bdesc->start =3D bdesc->end; - - /* start !=3D NULL means it is bit fields */ start =3D strtok(NULL, ":"); - if (start) - bdesc->start =3D strtoul(start, NULL, 0); - - strcpy(bdesc->simp, tokens[4]); - strcpy(bdesc->detail, tokens[5]); + bit_end =3D strtoul(end, NULL, 0); + bit_start =3D (start) ? strtoul(start, NULL, 0) : bit_end; + + for (sub =3D subleaf_start; sub <=3D subleaf_end; sub++) { + leaf =3D &func->leafs[sub]; + reg =3D &leaf->info[reg_index]; + bdesc =3D ®->descs[reg->nr++]; + + bdesc->end =3D bit_end; + bdesc->start =3D bit_start; + strcpy(bdesc->simp, strtok(tokens[4], " \t")); + strcpy(bdesc->detail, tokens[5]); + } return 0; =20 err_exit: @@ -452,8 +458,9 @@ static void decode_bits(u32 value, struct reg_desc *rdesc= , enum cpuid_reg reg) if (start =3D=3D end) { /* single bit flag */ if (value & (1 << start)) - printf("\t%-20s %s%s\n", + printf("\t%-20s %s%s%s\n", bdesc->simp, + show_flags_only ? "" : "\t\t\t", show_details ? "-" : "", show_details ? bdesc->detail : "" ); . Subject: [PATCH] perf/test: Speed up test case perf annotate basic tests From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, namhyung@kernel.org Cc: agordeev@linux.ibm.com, gor@linux.ibm.com, sumanthk@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Date: Tue, 17 Sep 2024 10:57:06 +0200 . Subject: [RFC PATCH v2 0/6] vfio: platform: reset: Introduce tegra234 mgbe reset module From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, treding@nvidia.com, vbhadram@nvidia.com, jonathanh@nvidia.com, mperttunen@nvidia.com, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, alex.williamson@redhat.com, clg@redhat.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com Cc: msalter@redhat.com Date: Tue, 17 Sep 2024 11:38:08 +0200 . Subject: [PATCH] crypto: algif_skcipher - Enable access to internal skciphers From: "Tomas Paukrt" To: Cc: "Herbert Xu" , "David S. Miller" , Date: Tue, 17 Sep 2024 11:20:12 +0200 (CEST) . Subject: [GIT pull] irq/domain for v6.12-rc1 From: Thomas Gleixner To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, x86@kernel.org Date: Tue, 17 Sep 2024 11:01:09 +0200 (CEST) Linus, please pull the latest irq/domain branch from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-domain-2024-= 09-17 up to: 74c60a96ef6a: irqdomain: Remove stray '-' in the domain name Two small updates for interrupt domains: - Remove a stray '-' in the domain name - Consolidate and clarify the bus token checks so they explicitely check for DOMAIN_BUS_ANY instead of unspecified checks for zero. Thanks, tglx ------------------> Andy Shevchenko (2): irqdomain: Clarify checks for bus_token irqdomain: Remove stray '-' in the domain name kernel/irq/irqdomain.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 01001eb615ec..1acc5308fcb7 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -130,8 +130,10 @@ EXPORT_SYMBOL_GPL(irq_domain_free_fwnode); =20 static int alloc_name(struct irq_domain *domain, char *base, enum irq_domain= _bus_token bus_token) { - domain->name =3D bus_token ? kasprintf(GFP_KERNEL, "%s-%d", base, bus_token= ) : - kasprintf(GFP_KERNEL, "%s", base); + if (bus_token =3D=3D DOMAIN_BUS_ANY) + domain->name =3D kasprintf(GFP_KERNEL, "%s", base); + else + domain->name =3D kasprintf(GFP_KERNEL, "%s-%d", base, bus_token); if (!domain->name) return -ENOMEM; =20 @@ -146,8 +148,10 @@ static int alloc_fwnode_name(struct irq_domain *domain, = const struct fwnode_hand const char *suf =3D suffix ? : ""; char *name; =20 - name =3D bus_token ? kasprintf(GFP_KERNEL, "%pfw-%s%s%d", fwnode, suf, sep,= bus_token) : - kasprintf(GFP_KERNEL, "%pfw-%s", fwnode, suf); + if (bus_token =3D=3D DOMAIN_BUS_ANY) + name =3D kasprintf(GFP_KERNEL, "%pfw%s%s", fwnode, sep, suf); + else + name =3D kasprintf(GFP_KERNEL, "%pfw%s%s-%d", fwnode, sep, suf, bus_token); if (!name) return -ENOMEM; =20 @@ -166,11 +170,13 @@ static int alloc_unknown_name(struct irq_domain *domain= , enum irq_domain_bus_tok static atomic_t unknown_domains; int id =3D atomic_inc_return(&unknown_domains); =20 - domain->name =3D bus_token ? kasprintf(GFP_KERNEL, "unknown-%d-%d", id, bus= _token) : - kasprintf(GFP_KERNEL, "unknown-%d", id); - + if (bus_token =3D=3D DOMAIN_BUS_ANY) + domain->name =3D kasprintf(GFP_KERNEL, "unknown-%d", id); + else + domain->name =3D kasprintf(GFP_KERNEL, "unknown-%d-%d", id, bus_token); if (!domain->name) return -ENOMEM; + domain->flags |=3D IRQ_DOMAIN_NAME_ALLOCATED; return 0; } @@ -200,7 +206,7 @@ static int irq_domain_set_name(struct irq_domain *domain,= const struct irq_domai return alloc_name(domain, fwid->name, bus_token); default: domain->name =3D fwid->name; - if (bus_token) + if (bus_token !=3D DOMAIN_BUS_ANY) return alloc_name(domain, fwid->name, bus_token); } =20 . Subject: [PATCH] perf sched replay: Remove unused parts of the code From: Madadi Vineeth Reddy To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Athira Rajeev , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , Kan Liang , acme@redhat.com, linux-perf-users , LKML Cc: Madadi Vineeth Reddy Date: Tue, 17 Sep 2024 14:31:00 +0530 . Subject: [PATCH 1/1] arm64: dts: qcom: qcs6490-rb3gen2: Add SD Card node From: Sachin Gupta To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Date: Tue, 17 Sep 2024 14:36:30 +0530 . Subject: [PATCH v2 0/2] PCI: mediatek-gen3: Support limiting link speed and width From: AngeloGioacchino Del Regno To: linux-pci@vger.kernel.org Cc: ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Date: Tue, 17 Sep 2024 11:11:30 +0200 . Subject: cpufreq/amd-pstate: Rename MSR and shared memory specific functions From: Dhananjay Ugwekar To: , , , , , Date: Tue, 17 Sep 2024 09:14:35 +0000 . Subject: [PATCH] perf sched timehist: Add pre-migration wait time option From: Madadi Vineeth Reddy To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Athira Rajeev , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , Kan Liang , acme@redhat.com, linux-perf-users , LKML Cc: Madadi Vineeth Reddy Date: Tue, 17 Sep 2024 14:45:37 +0530 . Subject: [PATCH] arm64: dts: qcom: qcs6460-rb3gen2: enable venus node From: Vedang Nagar via B4 Relay To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vedang Nagar Date: Tue, 17 Sep 2024 14:54:31 +0530 . Subject: [PATCH net-next v2 0/3] nic_basic_tests: Add selftest for doing basic tests of NIC driver From: Mohan Prasad J To: , , , Date: Tue, 17 Sep 2024 08:04:06 +0530 . Subject: [PATCH] crypto: lib/mpi - Extend support for scope-based resource management From: Markus Elfring To: kernel-janitors@vger.kernel.org, Herbert Xu Cc: LKML Date: Tue, 17 Sep 2024 11:33:14 +0200 . Subject: [GIT PULL] gpio updates for v6.12-rc1 From: Bartosz Golaszewski To: Linus Torvalds Cc: Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Date: Tue, 17 Sep 2024 11:39:56 +0200 From: Bartosz Golaszewski Linus, Here are the updates from the GPIO tree for the next release. We have one new driver, some improvements to core GPIO code, various changes in drivers and their DT bindings as well fixes to kerneldocs. Overall it has been a slow cycle, most likely due to the summertime vacation period and the changelog reflects it. The merge from the MFD tree is there to pull dependencies for the new driver. There is a trivial conflict with the SoC tree (just drop arch/arm/mach-ep93xx/vision_ep9307.c). Details are in the signed tag. Please pull. Bartosz Golaszewski The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git tags/gpio-updates-for-v6.12-rc1 for you to fetch changes up to 6b5e97c020060c2b8ad286002415106ab7034435: gpio: mpc8xxx: switch to using DEFINE_RUNTIME_DEV_PM_OPS() (2024-09-06 08:50:48 +0200) ---------------------------------------------------------------- gpio updates for v6.12-rc1 Core GPIOLIB: - provide and add users for a macro allowing to iterate over accepted GPIO property names of consumer device nodes - remove legacy definitions that are no longer used - put legacy GPIO devres helpers together with the rest of the deprecated code - implement and use swnode_gpio_get_reference(): a wrapper simplifying the underlying calls to fwnode_property_get_reference_args() - use IS_ERR_OR_NULL() where it makes sense - replace of_find_property() with of_property_present() - simplify code with the scoped variant of OF-node children iterator Documentation: - update GPIO kerneldocs with Return sections - fix "Excess struct member description" warnings now being triggered with W=1 New drivers: - add support for Analog Devices ADP5585 Driver improvements: - add support for wake-on-GPIO to gpio-mpc8xxx - use GPIO_LOOKUP_IDX() in gpio-virtuser - use devm_clk_get_[optional_]enabled() where applicable in several drivers - replace OF-specific functions with provider-agnostic alternatives where possible - drop support for legacy platform data from gpio-ath79 and gpio-davinci - refactor gpio-stmpe - improve error reporting in gpio-pca953x - add support for reading the direction of pins for some models to gpio-vf610 DT bindings: - convert the bindings for nxp,lpc3220 to YAML - add gpio-reserved-ranges to gpio-davinci - simplify the GPIO hog schema - fix a GPIO hog issue in bindings for fcs,fxl6408 Other: - fix format specifiers in user-space tools - remove leftover files on make clean in tools/gpio/ ---------------------------------------------------------------- Andy Shevchenko (22): gpiolib: Introduce for_each_gpio_property_name() helper gpiolib: swnode: Unify return code variable name gpiolib: swnode: Introduce swnode_gpio_get_reference() helper gpiolib: swnode: Make use of for_each_gpio_property_name() gpiolib: Replace gpio_suffix_count with NULL-terminated array gpio: virtuser: Use GPIO_LOOKUP_IDX() macro gpiolib: legacy: Kill GPIOF_INIT_* definitions gpiolib: legacy: Kill GPIOF_DIR_* definitions gpio: tegra: Replace of_node_to_fwnode() with more suitable API gpio: msc313: Replace of_node_to_fwnode() with more suitable API gpio: uniphier: Replace of_node_to_fwnode() with more suitable API gpio: tegra186: Replace of_node_to_fwnode() with more suitable API gpio: thunderx: Replace of_node_to_fwnode() with more suitable API gpio: visconti: Replace of_node_to_fwnode() with more suitable API gpio: ixp4xx: Replace of_node_to_fwnode() with more suitable API gpiolib: Update the kernel documentation - add Return sections gpiolib: legacy: Consolidate devm_gpio_*() with other legacy APIs gpio: stmpe: Fix IRQ related error messages gpio: stmpe: Remove unused 'dev' member of struct stmpe_gpio gpio: stmpe: Utilise temporary variable for struct device gpio: stmpe: Make use of device properties gpio: stmpe: Sort headers Animesh Agarwal (1): dt-bindings: gpio: nxp,lpc3220-gpio: Convert to dtschema Bartosz Golaszewski (9): Merge tag 'ib-mfd-gpio-pwm-v6.12' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next gpio: ath79: order headers alphabetically gpio: ath79: add missing header gpio: ath79: use generic device property getters gpio: ath79: remove support for platform data gpio: davinci: drop platform data support gpio: davinci: use devm_clk_get_enabled() gpio: mpc8xxx: order headers alphabetically gpio: mpc8xxx: switch to using DEFINE_RUNTIME_DEV_PM_OPS() Chen Ni (1): gpio: sama5d2-piobu: convert comma to semicolon Clark Wang (1): pwm: adp5585: Add Analog Devices ADP5585 support Dhruva Gole (1): gpio: syscon: fix excess struct member build warning Fabio Estevam (1): gpio: pca953x: Print the error code on read/write failures Haibo Chen (4): mfd: adp5585: Add Analog Devices ADP5585 core support gpio: adp5585: Add Analog Devices ADP5585 support gpio: gpio-vf610: use u32 mask to handle 32 number gpios gpio: vf610: add get_direction() support Hongbo Li (1): gpio: Use IS_ERR_OR_NULL() helper function Jared McArthur (1): dt-bindings: gpio: gpio-davinci: Add the gpio-reserved-ranges property Krzysztof Kozlowski (4): gpio: of: simplify with scoped for each OF child loop dt-bindings: gpio: fcs,fxl6408: add missing type to GPIO hogs dt-bindings: gpio: simplify GPIO hog nodes schema gpio: pch: kerneldoc fixes for excess members Laurent Pinchart (1): dt-bindings: mfd: Add Analog Devices ADP5585 Martyn Welch (1): gpio: mpc8xxx: Add wake on GPIO support Rob Herring (Arm) (1): gpio: Use of_property_present() Rong Qianfeng (2): gpio: stp-xway: Simplify using devm_clk_get_enabled() gpio: zynq: Simplify using devm_clk_get_enabled() Shen Lichuan (1): gpio: stmpe: Simplify with dev_err_probe() Uwe Kleine-König (1): gpio: Drop explicit initialization of struct i2c_device_id::driver_data to 0 Zhang Zekun (4): gpio: cadence: Use helper function devm_clk_get_enabled() gpio: lpc18xx: Use helper function devm_clk_get_enabled() gpio: mb86s7x: Use helper function devm_clk_get_optional_enabled() gpio: xilinx: Use helper function devm_clk_get_optional_enabled() Zhu Jun (1): tools: gpio: Fix the wrong format specifier zhangjiao (1): tools: gpio: rm .*.cmd on make clean .../bindings/gpio/fairchild,74hc595.yaml | 11 - .../devicetree/bindings/gpio/fcs,fxl6408.yaml | 1 + .../devicetree/bindings/gpio/fsl-imx-gpio.yaml | 11 - .../devicetree/bindings/gpio/gpio-davinci.yaml | 2 + .../devicetree/bindings/gpio/gpio-pca95xx.yaml | 11 - .../devicetree/bindings/gpio/gpio_lpc32xx.txt | 43 ---- .../bindings/gpio/microchip,mpfs-gpio.yaml | 12 -- .../devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml | 50 +++++ .../bindings/gpio/socionext,uniphier-gpio.yaml | 11 - .../devicetree/bindings/mfd/adi,adp5585.yaml | 92 +++++++++ .../devicetree/bindings/trivial-devices.yaml | 4 - MAINTAINERS | 11 + arch/arm/mach-ep93xx/vision_ep9307.c | 6 +- arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-adp5585.c | 229 +++++++++++++++++++++ drivers/gpio/gpio-ath79.c | 31 +-- drivers/gpio/gpio-cadence.c | 23 +-- drivers/gpio/gpio-davinci.c | 102 +++------ drivers/gpio/gpio-fxl6408.c | 2 +- drivers/gpio/gpio-ixp4xx.c | 10 +- drivers/gpio/gpio-lpc18xx.c | 23 +-- drivers/gpio/gpio-max7300.c | 2 +- drivers/gpio/gpio-mb86s7x.c | 21 +- drivers/gpio/gpio-mpc8xxx.c | 50 ++++- drivers/gpio/gpio-msc313.c | 5 +- drivers/gpio/gpio-pca953x.c | 4 +- drivers/gpio/gpio-pch.c | 1 - drivers/gpio/gpio-sama5d2-piobu.c | 18 +- drivers/gpio/gpio-stmpe.c | 55 ++--- drivers/gpio/gpio-stp-xway.c | 10 +- drivers/gpio/gpio-syscon.c | 1 - drivers/gpio/gpio-tegra.c | 5 +- drivers/gpio/gpio-tegra186.c | 3 +- drivers/gpio/gpio-thunderx.c | 5 +- drivers/gpio/gpio-uniphier.c | 5 +- drivers/gpio/gpio-vf610.c | 31 ++- drivers/gpio/gpio-virtuser.c | 13 +- drivers/gpio/gpio-visconti.c | 5 +- drivers/gpio/gpio-xilinx.c | 11 +- drivers/gpio/gpio-zynq.c | 10 +- drivers/gpio/gpiolib-acpi.c | 43 ++-- drivers/gpio/gpiolib-cdev.c | 8 +- drivers/gpio/gpiolib-devres.c | 120 ++++------- drivers/gpio/gpiolib-legacy.c | 94 ++++++++- drivers/gpio/gpiolib-of.c | 92 ++++----- drivers/gpio/gpiolib-swnode.c | 62 +++--- drivers/gpio/gpiolib-sysfs.c | 6 +- drivers/gpio/gpiolib.c | 164 +++++++++++---- drivers/gpio/gpiolib.h | 16 +- drivers/mfd/Kconfig | 12 ++ drivers/mfd/Makefile | 1 + drivers/mfd/adp5585.c | 205 ++++++++++++++++++ drivers/pwm/Kconfig | 7 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-adp5585.c | 184 +++++++++++++++++ include/linux/gpio.h | 12 +- include/linux/mfd/adp5585.h | 126 ++++++++++++ include/linux/platform_data/gpio-ath79.h | 16 -- include/linux/platform_data/gpio-davinci.h | 21 -- tools/gpio/Makefile | 2 +- tools/gpio/gpio-hammer.c | 4 +- 63 files changed, 1503 insertions(+), 643 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt create mode 100644 Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml create mode 100644 Documentation/devicetree/bindings/mfd/adi,adp5585.yaml create mode 100644 drivers/gpio/gpio-adp5585.c create mode 100644 drivers/mfd/adp5585.c create mode 100644 drivers/pwm/pwm-adp5585.c create mode 100644 include/linux/mfd/adp5585.h delete mode 100644 include/linux/platform_data/gpio-ath79.h delete mode 100644 include/linux/platform_data/gpio-davinci.h . Subject: [PATCH] dt-bindings: usb: genesys,gl850g: allow downstream device subnodes From: Icenowy Zheng To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng Date: Tue, 17 Sep 2024 17:40:08 +0800 . Subject: [GIT PULL] power sequencing updates for v6.12-rc1 From: Bartosz Golaszewski To: Linus Torvalds Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Date: Tue, 17 Sep 2024 11:45:57 +0200 From: Bartosz Golaszewski Linus, Please pull the following updates for the power sequencing subsystem. There's one change adding support for a new PMU model and another adding documentation for the subsystem which probably should have been part of the initial commit but better late than never. Details are in the signed tag. Thanks, Bartosz Golaszewski The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git tags/pwrseq-updates-for-v6.12-rc1 for you to fetch changes up to 8b7e0a6c443e855374a426dcdfd0a19912d70df3: Documentation: add a driver API doc for the power sequencing subsystem (2024-08-22 15:29:29 +0200) ---------------------------------------------------------------- power sequencing updates for v6.12-rc1 - add support for the new PMU variant inside the WCN6855 chipset - add documentation for the subsystem ---------------------------------------------------------------- Bartosz Golaszewski (1): Documentation: add a driver API doc for the power sequencing subsystem Konrad Dybcio (1): power: sequencing: qcom-wcn: add support for the WCN6855 PMU Documentation/driver-api/index.rst | 1 + Documentation/driver-api/pwrseq.rst | 95 ++++++++++++++++++++++++++++++ MAINTAINERS | 1 + drivers/power/sequencing/pwrseq-qcom-wcn.c | 11 ++++ 4 files changed, 108 insertions(+) create mode 100644 Documentation/driver-api/pwrseq.rst . Subject: [PATCH v3] dt-bindings: opp: operating-points-v2-ti-cpu: Describe opp-supported-hw From: Dhruva Gole To: Viresh Kumar , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Date: Tue, 17 Sep 2024 15:22:52 +0530 . Subject: [PATCH 1/2] dt-bindings: display: panel-simple: Document support for Microchip AC69T88A From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Date: Tue, 17 Sep 2024 15:23:29 +0530 . Subject: [PATCH v4 0/5] Add support for SPI-NOR Macronix OTP From: Erez Geva To: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle Cc: linux-kernel@vger.kernel.org, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Esben Haabendal , Erez Geva Date: Tue, 17 Sep 2024 11:49:51 +0200 . Subject: [PATCH] hid: hid-lenovo: Supporting TP-X12-TAB-1/2 Kbd Hotkeys using raw events. From: Vishnu Sankar To: jikos@kernel.org, bentiss@kernel.org, linux-input@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mpearson-lenovo@squebb.ca, vsankar@lenovo.com, Vishnu Sankar Date: Tue, 17 Sep 2024 19:04:31 +0900 . Subject: [PATCH 5.10] xhci: check virt_dev is valid before dereferencing it From: Roman Smirnov To: , Greg Kroah-Hartman Date: Tue, 17 Sep 2024 13:07:03 +0300 . Subject: [PATCH v3] usb: dwc3: gadget: Refine the logic for resizing Tx FIFOs From: Akash Kumar To: Thinh Nguyen , Greg Kroah-Hartman , Jing Leng , Felipe Balbi , Jack Pham , , Wesley Cheng , Laurent Pinchart , Daniel Scally Date: Tue, 17 Sep 2024 15:43:55 +0530 . Subject: [PATCH 5.10] regmap: cache: Add extra parameter check in regcache_init From: Roman Smirnov To: , Greg Kroah-Hartman , Sergey Shtylyov Date: Tue, 17 Sep 2024 13:17:57 +0300 . Subject: [PATCH 5.10] xhci: check virt_dev is valid before dereferencing it From: Roman Smirnov To: , Greg Kroah-Hartman Date: Tue, 17 Sep 2024 13:21:50 +0300 . Subject: [PATCH] arm64: dts: qcom: x1e80100-t14s: add another trackpad support From: srinivas.kandagatla@linaro.org To: andersson@kernel.org Cc: konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Date: Tue, 17 Sep 2024 06:27:15 -0400 . Subject: [PATCH] clk: samsung: fsd: Mark PLL_CAM_CSI as critical From: Inbaraj E To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: pankaj.dubey@samsung.com, gost.dev@samsung.com, Inbaraj E Date: Tue, 17 Sep 2024 15:40:16 +0530 . Subject: [PATCH 0/2] clk: samsung: remove number of clocks from bindings From: Inbaraj E To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: pankaj.dubey@samsung.com, gost.dev@samsung.com, Inbaraj E Date: Tue, 17 Sep 2024 15:13:53 +0530 . Subject: [PATCH] MAINTAINERS: adjust file entry in INTEL MID PLATFORM From: Lukas Bulwahn To: Andy Shevchenko , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , platform-driver-x86@vger.kernel.org Cc: kernel-janitors@vger.kernel.org, linux-kernel@vger.kernel.org, Lukas Bulwahn Date: Tue, 17 Sep 2024 12:39:55 +0200 . Subject: [PATCH v2] list: Remove duplicated and unused macro list_for_each_reverse From: Zijun Hu To: Greg Kroah-Hartman , Ingo Molnar Cc: Zijun Hu , linux-kernel@vger.kernel.org, Zijun Hu Date: Tue, 17 Sep 2024 18:42:56 +0800 . Subject: [PATCH] PCI: qcom: Skip wait for link up if global IRQ handler is present From: Krishna chaitanya chundru To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Date: Tue, 17 Sep 2024 16:16:20 +0530 . Subject: [PATCH] Bluetooth: btbcm: Handle memory allocation failure in btbcm_get_board_name() From: Aleksandr Mishin To: Linus Walleij Date: Tue, 17 Sep 2024 13:53:31 +0300 . Subject: [PATCH] nvmet: Remove unnecessary check in nvmet_sq_destroy() From: George Rurikov To: Christoph Hellwig Date: Tue, 17 Sep 2024 14:35:35 +0300 . Subject: [PATCH] kvm/debugfs: add file to get vcpu steal time statistics From: Denis Plotnikov To: kvm@vger.kernel.org Cc: seanjc@google.com, pbonzini@redhat.com, yc-core@yandex-team.ru, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 14:20:28 +0300 . Subject: [PATCH v4 00/11] Preemption support for A7XX From: Antonino Maniscalco To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Corbet Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Antonino Maniscalco , Akhil P Oommen , Neil Armstrong , Sharat Masetty Date: Tue, 17 Sep 2024 13:14:10 +0200 . Subject: [PATCH 5.10/5.15/6.1] Bluetooth: btbcm: Handle memory allocation failure in btbcm_get_board_name() From: Aleksandr Mishin To: Linus Walleij , , Greg Kroah-Hartman Date: Tue, 17 Sep 2024 14:14:22 +0300 . Subject: [PATCH v2] usb: gadget: u_ether: Use __netif_rx() in rx_callback() From: Hubert =?UTF-8?Q?Wi=C5=9Bniewski?= To: Greg Kroah-Hartman , Ferry Toth , Kees Cook , Justin Stitt , Richard Acayan , "Ricardo B. Marliere" , Hardik Gajjar , Jeff Johnson , Eric Dumazet , "David S. Miller" , Sebastian Andrzej Siewior , Toke =?ISO-8859-1?Q?H=F8iland-J=F8rgensen?= , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 13:19:25 +0200 . Subject: [PATCH] ata: pata_octeon_cf: Use common error handling code in octeon_cf_probe() From: Markus Elfring To: linux-ide@vger.kernel.org, Damien Le Moal , Niklas Cassel , Sergey Shtylyov Cc: LKML Date: Tue, 17 Sep 2024 13:50:09 +0200 . Subject: [PATCH net-next V4] net: phy: microchip_t1: SQI support for LAN887x From: Tarun Alle To: , , , , , , , , , , Date: Tue, 17 Sep 2024 17:26:57 +0530 . Subject: [PATCH 6.1] platform/x86: android-platform: deref after free in x86_android_tablet_init() fix From: Aleksandr Burakov To: Greg Kroah-Hartman , stable@vger.kernel.org, Hans de Goede , Mark Gross Cc: Aleksandr Burakov , linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org, lvc-patches@linuxtesting.org, platform-driver-x86@vger.kernel.org Date: Tue, 17 Sep 2024 15:04:58 +0300 . Subject: [PATCH][next] drm/nouveau/gsp: remove extraneous ; after mutex From: Colin Ian King To: Karol Herbst , Lyude Paul , Danilo Krummrich , David Airlie , Simona Vetter , Dave Airlie , Ben Skeggs , dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org Cc: kernel-janitors@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 13:08:56 +0100 . Subject: [PATCH] clk: at91: pmc: Use common error handling code in pmc_register_ops() From: Markus Elfring To: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Belloni , Claudiu Beznea , Michael Turquette , Nicolas Ferre , Stephen Boyd Cc: LKML Date: Tue, 17 Sep 2024 14:34:54 +0200 . Subject: [PATCH v3] drm/i915/cx0: Set power state to ready only on owned PHY lanes From: Vamsi Krishna Brahmajosyula To: gustavo.sousa@intel.com, jani.nikula@linux.intel.com, rodrigo.vivi@intel.com, joonas.lahtinen@linux.intel.com, tursulin@ursulin.net, airlied@gmail.com, daniel@ffwll.ch Cc: skhan@linuxfoundation.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 18:14:49 +0530 . Subject: [PATCH v2 0/2] pinctrl: ocelot: add support for lan969x SoC From: Daniel Machon To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Belloni , Lars Povlsen , Horatiu Vultur , Steen Hegelund Date: Tue, 17 Sep 2024 14:45:39 +0200 . Subject: [PATCH] clk: davinci: Use common error handling code in of_davinci_pll_init() From: Markus Elfring To: linux-clk@vger.kernel.org, David Lechner , Michael Turquette , Nishka Dasgupta , Stephen Boyd Cc: LKML Date: Tue, 17 Sep 2024 15:10:32 +0200 . Subject: [syzbot] [ocfs2?] INFO: trying to register non-static key in ocfs2_dlm_shutdown From: syzbot To: jlbec@evilplan.org, joseph.qi@linux.alibaba.com, linux-kernel@vger.kernel.org, mark@fasheh.com, ocfs2-devel@lists.linux.dev, syzkaller-bugs@googlegroups.com Date: Tue, 17 Sep 2024 06:24:30 -0700 . Subject: [PATCH] powerpc/pseries/eeh: move pseries_eeh_err_inject() outside CONFIG_DEBUG_FS block From: Narayana Murty N To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, linux-kernel@vger.kernel.org Cc: mahesh@linux.ibm.com, oohall@gmail.com, npiggin@gmail.com, christophe.leroy@csgroup.eu, naveen@kernel.org, vaibhav@linux.ibm.com, ganeshgr@linux.ibm.com, sbhat@linux.ibm.com Date: Tue, 17 Sep 2024 09:24:45 -0400 . Subject: [PATCH 5.10] Input: adp5588-keys - add support for fw properties From: Denis Arefev To: stable@vger.kernel.org, Greg Kroah-Hartman Cc: Dmitry Torokhov , Michael Hennerich , Andy Shevchenko , =?UTF-8?q?Nuno=20S=C3=A1?= , linux-kernel@vger.kernel.org, linux-input@vger.kernel.org, lvc-project@linuxtesting.org Date: Tue, 17 Sep 2024 16:29:45 +0300 . Subject: [PATCH] cpufreq: Avoid a bad reference count on CPU node From: =?UTF-8?q?Miquel=20Sabat=C3=A9=20Sol=C3=A0?= To: rafael@kernel.org Cc: viresh.kumar@linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Miquel=20Sabat=C3=A9=20Sol=C3=A0?= Date: Tue, 17 Sep 2024 15:42:46 +0200 . Subject: [GIT PULL] LKMM changes for v6.12 From: "Paul E. McKenney" To: torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, lkmm@lists.linux.dev, parri.andrea@gmail.com, akiyks@gmail.com, boqun.feng@gmail.com Date: Tue, 17 Sep 2024 06:49:05 -0700 Hello, Linus, Please pull this LKMM update from: git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git tags/lkmm.2024.09.14b # HEAD: a49f48cc7d26270bee727d30ce830d4129b33d4a: MAINTAINERS: Add the dedicated maillist info for LKMM (2024-09-13 23:56:44 -0700) ---------------------------------------------------------------- lkmm: Add documentation and mailing list This pull request contains documentation updates from Andrea Parri and Akira Yokosawa. Also, there is now an lkmm@lists.linux.dev, and Boqun Feng's update adds this to the LKMM MAINTAINERS entry. Not included in this pull request are a couple of more commits from Puranjay Mohan adding more atomic operations to LKMM, but these await a herdtools7 release that includes tool-side support for this functionality. With luck, I will send a separate pull request for these later in the merge window. ---------------------------------------------------------------- Akira Yokosawa (3): tools/memory-model: Add locking.txt and glossary.txt to README tools/memory-model: simple.txt: Fix stale reference to recipes-pairs.txt docs/memory-barriers.txt: Remove left-over references to "CACHE COHERENCY" Andrea Parri (1): tools/memory-model: Document herd7 (abstract) representation Boqun Feng (1): MAINTAINERS: Add the dedicated maillist info for LKMM Documentation/memory-barriers.txt | 3 - MAINTAINERS | 1 + tools/memory-model/Documentation/README | 24 ++++- .../Documentation/herd-representation.txt | 110 +++++++++++++++++++++ tools/memory-model/Documentation/simple.txt | 2 +- 5 files changed, 135 insertions(+), 5 deletions(-) create mode 100644 tools/memory-model/Documentation/herd-representation.txt . Subject: [PATCH v3] usb: gadget: u_ether: Use __netif_rx() in rx_callback() From: Hubert =?UTF-8?Q?Wi=C5=9Bniewski?= To: Greg Kroah-Hartman , Ferry Toth , Hardik Gajjar , Kees Cook , Justin Stitt , Richard Acayan , Jeff Johnson , "Ricardo B. Marliere" , "David S. Miller" , Eric Dumazet , Toke =?ISO-8859-1?Q?H=F8iland-J=F8rgensen?= , Sebastian Andrzej Siewior , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 15:56:33 +0200 . Subject: [PATCH] V4L/DVB (13661): rj54n1cb0c: possible integer overflow fix From: Aleksandr Burakov To: Mauro Carvalho Chehab , Guennadi Liakhovetski Cc: Aleksandr Burakov , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org, lvc-patches@linuxtesting.org Date: Tue, 17 Sep 2024 17:04:54 +0300 . Subject: [PATCH 0/4] media: v4l2-subdev: Add cleanup macros for active state From: Tomi Valkeinen To: Mauro Carvalho Chehab , =?utf-8?q?Niklas_S=C3=B6derlund?= , Hans Verkuil , Sakari Ailus , Laurent Pinchart Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Tomi Valkeinen Date: Tue, 17 Sep 2024 17:09:28 +0300 . Subject: [PATCH 00/23] kbuild: support building external modules in a separate build directory From: Masahiro Yamada To: linux-kbuild@vger.kernel.org Cc: Miguel Ojeda , rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, Nathan Chancellor , Nicolas Schier , Masahiro Yamada Date: Tue, 17 Sep 2024 23:16:28 +0900 . Subject: [RFC PATCH 0/4] Add hazard pointers to kernel From: Boqun Feng To: linux-kernel@vger.kernel.org, rcu@vger.kernel.org, linux-mm@kvack.org, lkmm@vger.kernel.org Cc: "Paul E. McKenney" , Frederic Weisbecker , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , Boqun Feng , Uladzislau Rezki , Steven Rostedt , Mathieu Desnoyers , Lai Jiangshan , Zqiang , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Mark Rutland , Thomas Gleixner , Kent Overstreet , Linus Torvalds , Vlastimil Babka , maged.michael@gmail.com Date: Tue, 17 Sep 2024 07:33:58 -0700 . Subject: [PATCH 5.10] mtd: rawnand: mxc: Remove platform data support From: Denis Arefev To: stable@vger.kernel.org, Greg Kroah-Hartman Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Fabio Estevam , Sascha Hauer , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, lvc-project@linuxtesting.org Date: Tue, 17 Sep 2024 17:47:33 +0300 . Subject: [syzbot] [udf?] KMSAN: uninit-value in udf_get_fileshortad From: syzbot To: jack@suse.com, linux-kernel@vger.kernel.org, syzkaller-bugs@googlegroups.com Date: Tue, 17 Sep 2024 07:52:34 -0700 . Subject: [PATCH -fixes] riscv: Fix kernel stack size when KASAN is enabled From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , syzbot+ba9eac24453387a9d502@syzkaller.appspotmail.com, stable@vger.kernel.org Date: Tue, 17 Sep 2024 17:03:28 +0200 . Subject: [PATCH RFC] blktrace: add i/o alignment information From: Daniel Gomez via B4 Relay To: Jens Axboe , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers Cc: linux-block@vger.kernel.org, linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org, gost.dev@samsung.com, John Garry , Dave Chinner , Luis Chamberlain , Pankaj Raghav , Dan Helmick , Daniel Gomez , Daniel Gomez Date: Tue, 17 Sep 2024 17:22:18 +0200 . Subject: [PATCH v2] arm64: dts: qcom: x1e80100-t14s: add another trackpad support From: srinivas.kandagatla@linaro.org To: andersson@kernel.org Cc: konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, abel.vesa@linaro.org, Srinivas Kandagatla Date: Tue, 17 Sep 2024 11:00:49 -0400 . Subject: [PATCH] drm/bridge: imx: Use of_node_put(remote) call only once in imx8qxp_pc_bridge_probe() From: Markus Elfring To: imx@lists.linux.dev, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de, Andrzej Hajda , David Airlie , Fabio Estevam , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Liu Ying , Maarten Lankhorst , Maxime Ripard , Neil Armstrong , Robert Foss , Sascha Hauer , Shawn Guo , Simona Vetter , Thomas Zimmermann Cc: LKML Date: Tue, 17 Sep 2024 17:00:31 +0200 . Subject: [PATCH] wifi: mwifiex: Fix memcpy() field-spanning write warning in mwifiex_config_scan() From: Alper Nebi Yasak To: linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org Cc: David Lin , Dmitry Antipov , Brian Norris , Kalle Valo , Francesco Dolcini , Sascha Hauer , Kees Cook , "Gustavo A . R . Silva" , Andy Shevchenko , Johannes Berg , Alper Nebi Yasak Date: Tue, 17 Sep 2024 18:08:41 +0300 . Subject: [PATCH 0/4] Add support for new IMX8MP based board From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Shawn Guo , Petr Benes Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Herburger , Hiago De Franco , Hugo Villeneuve , Joao Paulo Goncalves , Michael Walle , Alexander Stein , Mathieu Othacehe , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 17 Sep 2024 17:09:57 +0200 . Subject: [PATCH v3 0/7] Lazy flush for the auth session From: Jarkko Sakkinen To: linux-integrity@vger.kernel.org Cc: James.Bottomley@HansenPartnership.com, roberto.sassu@huawei.com, mapengyu@gmail.com, Jarkko Sakkinen , Mimi Zohar , David Howells , Paul Moore , James Morris , "Serge E. Hallyn" , keyrings@vger.kernel.org, linux-security-module@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 18:44:29 +0300 . Subject: [GIT PULL] fbdev fixes and cleanups for v6.12-rc1 From: Helge Deller To: Linus Torvalds , linux-kernel@vger.kernel.org, linux-fbdev@vger.kernel.org, dri-devel@lists.freedesktop.org Date: Tue, 17 Sep 2024 17:45:40 +0200 Hi Linus, please pull some updates and cleanups for the fbdev drivers for kernel 6.12-rc1. This patchset includes a crashfix for xen and a possible use-after-free fix in pxafb. Thanks! Helge ---------------------------------------------------------------- The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b: Linux 6.11-rc1 (2024-07-28 14:19:55 -0700) are available in the Git repository at: http://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git tags/fbdev-for-6.12-rc1 for you to fetch changes up to de5e89b6654ea0b021a5737e0f55fc6bed625550: fbdev: omapfb: Fix typo in comment (2024-09-11 20:53:04 +0200) ---------------------------------------------------------------- fbdev fixes and updates for 6.12-rc1: - video: Reduce code when CONFIG_HAS_IOPORT=n - xenfb: Fix crash by assigning fb_info->device - pxafb: Fix possible use after free in pxafb_task() - efifb: Introduce and use new devm_register_framebuffer() function - mmpfb: Utilize devm_clk_get_enabled() helpers - various typo fixes and code cleanups ---------------------------------------------------------------- Andrew Kreimer (1): fbdev: omapfb: Fix typo in comment Chen Ni (3): fbdev: pxa3xx-gcu: Convert comma to semicolon fbdev: imsttfb: convert comma to semicolon fbdev: hyperv_fb: Convert comma to semicolon Christophe JAILLET (3): fbdev: hpfb: Fix an error handling path in hpfb_dio_probe() fbdev: omapfb: panel-sony-acx565akm: Simplify show_cabc_available_modes() fbdev: omapfb: Use sysfs_emit_at() to simplify code Jason Andryuk (1): fbdev: xen-fbfront: Assign fb_info->device Kaixin Wang (1): fbdev: pxafb: Fix possible use after free in pxafb_task() Niklas Schnelle (1): video: Handle HAS_IOPORT dependencies Thomas Weißschuh (4): fbdev: Introduce devm_register_framebuffer() fbdev: efifb: Register sysfs groups through driver core fbdev: efifb: Use devm_register_framebuffer() fbdev: efifb: Use driver-private screen_info for sysfs ying zuxin (1): fbdev: mmp: Use devm_clk_get_enabled() helpers drivers/video/fbdev/core/fbmem.c | 30 +++++++++++ drivers/video/fbdev/efifb.c | 27 +++------- drivers/video/fbdev/hpfb.c | 1 + drivers/video/fbdev/hyperv_fb.c | 2 +- drivers/video/fbdev/imsttfb.c | 4 +- drivers/video/fbdev/mmp/hw/mmp_ctrl.c | 6 +-- drivers/video/fbdev/omap/omapfb_main.c | 36 ++++++-------- .../omap2/omapfb/displays/panel-sony-acx565akm.c | 15 +++--- drivers/video/fbdev/omap2/omapfb/dss/hdmi.h | 2 +- drivers/video/fbdev/pxa3xx-gcu.c | 4 +- drivers/video/fbdev/pxafb.c | 1 + drivers/video/fbdev/xen-fbfront.c | 1 + include/linux/fb.h | 1 + include/video/vga.h | 58 ++++++++++++++++------ 14 files changed, 111 insertions(+), 77 deletions(-) . Subject: [PATCH v3] x86/resctrl: Annotate get_mem_config() functions as __init From: Nathan Chancellor To: Fenghua Yu , Reinette Chatre , x86@kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen Cc: linux-kernel@vger.kernel.org, llvm@lists.linux.dev, patches@lists.linux.dev, Nathan Chancellor Date: Tue, 17 Sep 2024 09:02:53 -0700 . Subject: [GIT PULL] TPM DEVICE DRIVER: tpmdd-next-6.12-rc1 From: "Jarkko Sakkinen" To: "Linus Torvalds" Cc: "Peter Huewe" , "Jason Gunthorpe" , "David Howells" , , , Date: Tue, 17 Sep 2024 19:15:28 +0300 The following changes since commit 2f27fce67173bbb05d5a0ee03dae5c021202c912= : Merge tag 'sound-6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g= it/tiwai/sound (2024-09-17 17:03:43 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git tags= /tpmdd-next-6.12-rc1 for you to fetch changes up to f168c000d27f8134160d4a52dfc474a948a3d7e9: tpm: export tpm2_sessions_init() to fix ibmvtpm building (2024-09-17 18:5= 6:37 +0300) ---------------------------------------------------------------- Hi, Just updates and fixes, no major changes. I might send a PR during the release cycle addressing a performance issue i= n the bus encryption: 1. https://bugzilla.kernel.org/show_bug.cgi?id=3D219229 2. https://lore.kernel.org/linux-integrity/20240917154444.702370-1-jarkko@k= ernel.org/ The first version of the patch set cut out already five seconds and I expect similar figures from the current version but I really need some more feedback. However, this week is not exactly optimal for getting it, given the Vienna conference. BR, Jarkko ---------------------------------------------------------------- Jonathan McDowell (1): tpm: Clean up TPM space after command failure Kexy Biscuit (1): tpm: export tpm2_sessions_init() to fix ibmvtpm building Michal Suchanek (2): MAINTAINERS: Add selftest files to TPM section selftests: tpm2: test_smoke: Run only when TPM2 is avaialable. Uwe Kleine-K=C3=B6nig (1): tpm: Drop explicit initialization of struct i2c_device_id::driver_dat= a to 0 MAINTAINERS | 1 + drivers/char/tpm/st33zp24/i2c.c | 2 +- drivers/char/tpm/tpm-dev-common.c | 2 ++ drivers/char/tpm/tpm2-sessions.c | 1 + drivers/char/tpm/tpm2-space.c | 3 +++ drivers/char/tpm/tpm_i2c_atmel.c | 2 +- drivers/char/tpm/tpm_tis_i2c.c | 2 +- tools/testing/selftests/tpm2/test_smoke.sh | 2 ++ 8 files changed, 12 insertions(+), 3 deletions(-) . Subject: [PATCH 1/1] dmaengine: amd: qdma: Remove using the private get and set dma_ops APIs From: Lizhi Hou To: , Date: Tue, 17 Sep 2024 09:17:40 -0700 . Subject: [GIT PULL] parisc architecture fixes and updates for v6.12-rc1 From: Helge Deller To: Linus Torvalds , linux-kernel@vger.kernel.org, linux-parisc@vger.kernel.org, James Bottomley , John David Anglin Date: Tue, 17 Sep 2024 18:31:19 +0200 Hi Linus, Please pull the parisc architecture fixes and updates for 6.12-rc1, which includes: - On parisc we now use the generic clockevent framework for timekeeping. - Although there is no 64-bit glibc/userspace for parisc yet, for testing purposes one can run statically linked 64-bit binaries. This patchset contains two patches which fix 64-bit userspace which has been broken since kernel 4.19. - Fix the userspace stack position and size when the ADDR_NO_RANDOMIZE personality is enabled. - On other architectures mmap(MAP_GROWSDOWN | MAP_STACK) creates a downward-growing stack. On parisc mmap(MAP_STACK) is now sufficient to create an upward-growing stack. Thanks! Helge ---------------------------------------------------------------- The following changes since commit da3ea35007d0af457a0afc87e84fddaebc4e0b63: Linux 6.11-rc7 (2024-09-08 14:50:28 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git tags/parisc-for-6.12-rc1 for you to fetch changes up to 5d698966fa7b452035c44c937d704910bf3440dd: parisc: Allow mmap(MAP_STACK) memory to automatically expand upwards (2024-09-16 23:01:43 +0200) ---------------------------------------------------------------- parisc architecture fixes and updates for kernel v6.12-rc1: - Convert parisc to the generic clockevents framework - Fix syscall and mm for 64-bit userspace - Fix stack start when ADDR_NO_RANDOMIZE personality is set - Fix mmap(MAP_STACK) to map upward growing expandable memory on parisc ---------------------------------------------------------------- Helge Deller (6): parisc: Convert to generic clockevents parisc: Fix stack start for ADDR_NO_RANDOMIZE personality parisc: Fix 64-bit userspace syscall path parisc: Fix itlb miss handler for 64-bit programs parisc: Use PRIV_USER instead of hardcoded value parisc: Allow mmap(MAP_STACK) memory to automatically expand upwards Hongbo Li (1): parisc: pdc_stable: Constify struct kobj_type arch/parisc/Kconfig | 2 +- arch/parisc/include/asm/mman.h | 14 ++ arch/parisc/include/asm/processor.h | 2 +- arch/parisc/kernel/entry.S | 6 +- arch/parisc/kernel/smp.c | 2 +- arch/parisc/kernel/syscall.S | 14 +- arch/parisc/kernel/time.c | 261 +++++++++++++++--------------------- arch/parisc/kernel/traps.c | 2 +- drivers/parisc/pdc_stable.c | 2 +- fs/exec.c | 3 +- 10 files changed, 136 insertions(+), 172 deletions(-) . Subject: [PATCH] drm/amd/display: Fix unnecessary cast warnings from checkpatch From: Rohit Chavan To: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan , David Airlie , Daniel Vetter , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Rohit Chavan Date: Tue, 17 Sep 2024 22:01:19 +0530 . Subject: [PATCH v2] crash, powerpc: Default to CRASH_DUMP=n on PPC_BOOK3S_32 From: Dave Vasilevsky To: glaubitz@physik.fu-berlin.de, bhe@redhat.com, linuxppc-dev@lists.ozlabs.org, linux-sh@vger.kernel.org, mpe@ellerman.id.au, kexec@lists.infradead.org, linux-kernel@vger.kernel.org, ebiederm@xmission.com Cc: Dave Vasilevsky , =?UTF-8?q?Reimar=20D=C3=B6ffinger?= Date: Tue, 17 Sep 2024 12:37:20 -0400 . Subject: [PATCH] MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer From: Nikita Shubin To: soc@kernel.org, Alexander Sverdlin , Arnd Bergmann Cc: linux-kernel@vger.kernel.org, Nikita Shubin Date: Tue, 17 Sep 2024 19:34:01 +0300 . Subject: [syzbot] [bcachefs?] WARNING: suspicious RCU usage in bch2_snapshot_tree_oldest_subvol From: syzbot To: kent.overstreet@linux.dev, linux-bcachefs@vger.kernel.org, linux-kernel@vger.kernel.org, syzkaller-bugs@googlegroups.com Date: Tue, 17 Sep 2024 09:42:29 -0700 . Subject: [PATCH v3] drm/mediatek: ovl: Add fmt_convert function pointer to driver data From: Jason-JH.Lin To: Alper Nebi Yasak , Chun-Kuang Hu , AngeloGioacchino Del Regno Date: Wed, 18 Sep 2024 00:44:34 +0800 . Subject: [PATCH] usb: using mutex lock and supporting O_NONBLOCK flag in iowarrior_read() From: Jeongjun Park To: gregkh@linuxfoundation.org, oneukum@suse.com Cc: colin.i.king@gmail.com, aha310510@gmail.com, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Date: Wed, 18 Sep 2024 01:48:20 +0900 . Subject: [PATCH] cifs: Fix reversion of the iter in cifs_readv_receive(). From: David Howells To: Steve French , Christian Brauner Date: Tue, 17 Sep 2024 18:30:54 +0100 . Subject: [PATCH v2 0/5] Congatec Board Controller drivers From: Thomas Richard To: Lee Jones , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org, thomas.petazzoni@bootlin.com, blake.vermeer@keysight.com, Thomas Richard Date: Tue, 17 Sep 2024 19:00:46 +0200 . Subject: [GIT PULL] dlm updates for 6.12 From: David Teigland To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, gfs2@lists.linux.dev Date: Tue, 17 Sep 2024 12:05:50 -0500 Hi Linus, Please pull dlm updates from tag: git://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm.git dlm-6.12 Summary: - Remove some unnecesary hold/unhold rsb refcounting in cases where an existing refcount is known to exist. - Remove some unnecessary checking for zero nodeids, which should never exist, and add some warning if they do. - Make the slow freeing of structs in release_lockspace() async, run from a workqueue. - Prior rcu freeing allows some further struct lookups to run without a lock. - Use blocking kernel_connect on sockets to avoid EINPROGRESS. Thanks, Dave Alexander Aring (11): dlm: cleanup memory allocation helpers dlm: remove unnecessary refcounts dlm: never return invalid nodeid by dlm_our_nodeid() dlm: warn about invalid nodeid comparsions dlm: drop kobject release callback handling dlm: async freeing of lockspace resources dlm: use RSB_HASHED to avoid lookup twice dlm: move dlm_search_rsb_tree() out of lock dlm: move lkb xarray lookup out of lock dlm: do synchronized socket connect call dlm: add missing -ENOMEM if alloc_workqueue() fails fs/dlm/config.c | 2 +- fs/dlm/dlm_internal.h | 5 ++ fs/dlm/lock.c | 134 +++++++++++++++++++++++++++----------------------- fs/dlm/lock.h | 2 + fs/dlm/lockspace.c | 97 ++++++++++++++++++------------------ fs/dlm/lowcomms.c | 36 +------------- fs/dlm/main.c | 12 +++++ fs/dlm/member.c | 2 + fs/dlm/memory.c | 28 +++++------ fs/dlm/memory.h | 4 +- fs/dlm/recover.c | 9 ++-- 11 files changed, 164 insertions(+), 167 deletions(-) . Subject: [PATCH 00/15] fsi: Fixes and improvements From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, alistair@popple.id.au, joel@jms.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, eajames@linux.ibm.com, ninad@linux.ibm.com Date: Tue, 17 Sep 2024 12:16:32 -0500 . Subject: [PATCH] staging: vt6656: Update maintainer in TODO From: =?utf-8?Q?Dominik_Karol_Pi=C4=85tkowski?= To: philipp.g.hortmann@gmail.com, gregkh@linuxfoundation.org Cc: linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, =?utf-8?Q?Dominik_Karol_Pi=C4=85tkowski?= Date: Tue, 17 Sep 2024 17:19:55 +0000 . Subject: [PATCH 0/2] drm/mediatek: Adjustments for mtk_gem_prime_vmap() From: Markus Elfring To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Alexandre Mergnat , Angelo Gioacchino Del Regno , Chen-Yu Tsai , Chun-Kuang Hu , David Airlie , Matthias Brugger , Philipp Zabel , Simona Vetter , Sui Jingfeng , Thomas Zimmermann Cc: LKML Date: Tue, 17 Sep 2024 19:34:03 +0200 . Subject: [PATCH 0/6] Add support for the RZ/V2H Interrupt Control Unit From: Fabrizio Castro To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Michael Turquette , Stephen Boyd , Philipp Zabel , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , Lad Prabhakar , Marc Zyngier , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das Date: Tue, 17 Sep 2024 18:32:43 +0100 . Subject: [PATCH] ocfs2: Fix typo in comment From: Mohammed Anees To: ocfs2-devel@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Mark Fasheh , Joel Becker , Joseph Qi , Mohammed Anees Date: Tue, 17 Sep 2024 18:51:56 +0000 . Subject: drivers/gpu/drm/omapdrm/dss/dispc.c:4881:27: warning: stack frame size (2056) exceeds limit (2048) in 'dispc_runtime_resume' From: kernel test robot To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Tomi Valkeinen Date: Wed, 18 Sep 2024 03:08:20 +0800 . Subject: Prebuilt LLVM 19.1.0 uploaded From: Nathan Chancellor To: llvm@lists.linux.dev, linux-kernel@vger.kernel.org Cc: conor@kernel.org, ojeda@kernel.org Date: Tue, 17 Sep 2024 12:10:36 -0700 . Subject: [PATCH v6 1/1] pwm: imx27: workaround of the pwm output bug when decrease the duty cycle From: Frank Li To: marex@denx.de Cc: Frank.Li@nxp.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, francesco@dolcini.it, imx@lists.linux.dev, jun.li@nxp.com, kernel@pengutronix.de, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, p.zabel@pengutronix.de, pratikmanvar09@gmail.com, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org, ukleinek@kernel.org, xiaoning.wang@nxp.com Date: Tue, 17 Sep 2024 15:25:10 -0400 . Subject: [PATCH] driver core: fix async device shutdown hang From: Stuart Hayes To: linux-kernel@vger.kernel.org, Greg Kroah-Hartman , "Rafael J . Wysocki" , Martin Belanger , Oliver O'Halloran , Daniel Wagner , Keith Busch , Lukas Wunner , David Jeffery , Jeremy Allison , Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-nvme@lists.infradead.org, Nathan Chancellor , Jan Kiszka Cc: Stuart Hayes Date: Tue, 17 Sep 2024 15:15:17 -0500 . Subject: [PATCH v2 0/3] Add SEV-SNP CipherTextHiding feature support From: Ashish Kalra To: , , , , , , , Date: Tue, 17 Sep 2024 20:15:13 +0000 . Subject: [PATCH v6 0/2] btrfs: Don't block system suspend during fstrim From: Luca Stefani To: Cc: Luca Stefani , Chris Mason , Josef Bacik , David Sterba , linux-btrfs@vger.kernel.org, linux-kernel@vger.kernel.org Date: Tue, 17 Sep 2024 22:33:03 +0200 . Subject: [PATCH] mm: x86: instrument __get/__put_kernel_nofault From: Sabyrzhan Tasbolatov To: tglx@linutronix.de, bp@alien8.de, glider@google.com, andreyknvl@gmail.com, akpm@linux-foundation.org Cc: mingo@redhat.com, dave.hansen@linux.intel.com, ryabinin.a.a@gmail.com, x86@kernel.org, hpa@zytor.com, dvyukov@google.com, vincenzo.frascino@arm.com, brauner@kernel.org, dhowells@redhat.com, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, snovitoll@gmail.com Date: Wed, 18 Sep 2024 01:18:17 +0500 . Subject: [PATCH 5.10.y] genirq/ipi: Fix NULL pointer deref in irq_data_get_affinity_mask() From: Sergey Shtylyov To: , Date: Tue, 17 Sep 2024 23:30:39 +0300 . Subject: [PATCH 0/3] DRM/MSM: Support for Adreno 663 GPU From: Akhil P Oommen To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Daniel Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Date: Wed, 18 Sep 2024 02:08:40 +0530 . Subject: linux-next: Signed-off-by missing for commit in the kbuild tree From: Stephen Rothwell To: Masahiro Yamada Cc: Linux Kernel Mailing List , Linux Next Mailing List Date: Wed, 18 Sep 2024 06:41:36 +1000 . Subject: Re: [PATCH 1/7] block: change wait on bd_claiming to use a var_waitqueue, not a bit_waitqueue From: "NeilBrown" To: "Jens Axboe" Cc: "Ingo Molnar" , "Peter Zijlstra" , "Linus Torvalds" , linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-block@vger.kernel.org Date: Wed, 18 Sep 2024 07:54:05 +1000 . Subject: [PATCH] cpuidle: Fix reference count on CPU node From: =?UTF-8?q?Miquel=20Sabat=C3=A9=20Sol=C3=A0?= To: rafael@kernel.org Cc: daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Miquel=20Sabat=C3=A9=20Sol=C3=A0?= Date: Tue, 17 Sep 2024 23:13:25 +0200 . Subject: linux-next: duplicate patches in the btrfs tree From: Stephen Rothwell To: David Sterba Cc: Linux Kernel Mailing List , Linux Next Mailing List Date: Wed, 18 Sep 2024 07:53:27 +1000 .