Date: Thu, 27 Jun 2024 07:54:05 +0800 From: kernel test robot To: Niklas Cassel Cc: oe-kbuild-all@lists.linux.dev, linux-pci@vger.kernel.org, Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= Subject: [pci:controller/rockchip 11/11] drivers/pci/controller/dwc/pcie-dw-rockchip.c:491:undefined reference to `pci_epc_init_notify' Message-ID: <202406270721.a8SQi2hn-lkp@intel.com> X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Xref: photonic.trudheim.com org.kernel.vger.linux-pci:144562 Newsgroups: org.kernel.vger.linux-pci,dev.linux.lists.oe-kbuild-all Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail tree: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git controller/rockchip head: 246afbe0f6fca433d8d918b740719170b1b082cc commit: 246afbe0f6fca433d8d918b740719170b1b082cc [11/11] PCI: dw-rockchip: Use pci_epc_init_notify() directly config: loongarch-randconfig-r081-20240626 (https://download.01.org/0day-ci/archive/20240627/202406270721.a8SQi2hn-lkp@intel.com/config) compiler: loongarch64-linux-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406270721.a8SQi2hn-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202406270721.a8SQi2hn-lkp@intel.com/ All errors (new ones prefixed by >>): loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_init_notify': drivers/pci/controller/dwc/pcie-designware-ep.c:26:(.text+0x1e4): undefined reference to `pci_epc_init_notify' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_deinit': drivers/pci/controller/dwc/pcie-designware-ep.c:640:(.text+0x83c): undefined reference to `pci_epc_mem_free_addr' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:643:(.text+0x854): undefined reference to `pci_epc_mem_exit' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_linkup': drivers/pci/controller/dwc/pcie-designware-ep.c:811:(.text+0x924): undefined reference to `pci_epc_linkup' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_linkdown': drivers/pci/controller/dwc/pcie-designware-ep.c:836:(.text+0x964): undefined reference to `pci_epc_linkdown' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.o: in function `dw_pcie_ep_init': drivers/pci/controller/dwc/pcie-designware-ep.c:875:(.text+0xe90): undefined reference to `__devm_pci_epc_create' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:888:(.text+0xf20): undefined reference to `pci_epc_mem_init' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:895:(.text+0xf54): undefined reference to `pci_epc_mem_alloc_addr' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-designware-ep.c:906:(.text+0xf74): undefined reference to `pci_epc_mem_exit' loongarch64-linux-ld: drivers/pci/controller/dwc/pcie-dw-rockchip.o: in function `rockchip_pcie_configure_ep': >> drivers/pci/controller/dwc/pcie-dw-rockchip.c:491:(.text+0x7cc): undefined reference to `pci_epc_init_notify' vim +491 drivers/pci/controller/dwc/pcie-dw-rockchip.c 441 442 static int rockchip_pcie_configure_ep(struct platform_device *pdev, 443 struct rockchip_pcie *rockchip) 444 { 445 struct device *dev = &pdev->dev; 446 int irq, ret; 447 u32 val; 448 449 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP)) 450 return -ENODEV; 451 452 irq = platform_get_irq_byname(pdev, "sys"); 453 if (irq < 0) { 454 dev_err(dev, "missing sys IRQ resource\n"); 455 return irq; 456 } 457 458 ret = devm_request_threaded_irq(dev, irq, NULL, 459 rockchip_pcie_ep_sys_irq_thread, 460 IRQF_ONESHOT, "pcie-sys", rockchip); 461 if (ret) { 462 dev_err(dev, "failed to request PCIe sys IRQ\n"); 463 return ret; 464 } 465 466 /* LTSSM enable control mode */ 467 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); 468 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); 469 470 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE, 471 PCIE_CLIENT_GENERAL_CONTROL); 472 473 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; 474 rockchip->pci.ep.page_size = SZ_64K; 475 476 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 477 478 ret = dw_pcie_ep_init(&rockchip->pci.ep); 479 if (ret) { 480 dev_err(dev, "failed to initialize endpoint\n"); 481 return ret; 482 } 483 484 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep); 485 if (ret) { 486 dev_err(dev, "failed to initialize DWC endpoint registers\n"); 487 dw_pcie_ep_deinit(&rockchip->pci.ep); 488 return ret; 489 } 490 > 491 pci_epc_init_notify(rockchip->pci.ep.epc); 492 493 /* unmask DLL up/down indicator and hot reset/link-down reset */ 494 rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC); 495 496 return ret; 497 } 498 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki . From: Lorenzo Bianconi To: linux-pci@vger.kernel.org Cc: ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi83@gmail.com, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, nbd@nbd.name, dd@embedd.com, upstream@airoha.com, angelogioacchino.delregno@collabora.com Subject: [PATCH v2 0/4] Add Airoha EN7581 PCIe support Date: Thu, 27 Jun 2024 10:12:10 +0200 Message-ID: X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Xref: photonic.trudheim.com org.kernel.vger.linux-pci:144570 Newsgroups: org.kernel.vger.linux-pci,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-mediatek,org.kernel.vger.linux-devicetree Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail Introduce support for EN7581 SoC to mediatek-gen3 PCIe driver Changes since v1: - remove register magic values - remove delay magic values - cosmetics - fix dts binding for clock/reset Lorenzo Bianconi (4): dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581 PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines PCI: mediatek-gen3: Add Airoha EN7581 support .../bindings/pci/mediatek-pcie-gen3.yaml | 68 +++++++- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek-gen3.c | 163 ++++++++++++++++-- 3 files changed, 212 insertions(+), 21 deletions(-) -- 2.45.2 . From: Herve Codina To: Andy Shevchenko , Simon Horman , Herve Codina , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Arnd Bergmann , UNGLinuxDriver@microchip.com, Saravana Kannan , Bjorn Helgaas , Philipp Zabel , Lars Povlsen , Steen Hegelund , Daniel Machon Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Andrew Lunn , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Allan Nielsen , Steen Hegelund , Luca Ceresoli , Thomas Petazzoni Subject: [PATCH v3 0/7] Add support for the LAN966x PCI device using a DT overlay Date: Thu, 27 Jun 2024 11:11:29 +0200 Message-ID: <20240627091137.370572-1-herve.codina@bootlin.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xref: photonic.trudheim.com org.kernel.vger.linux-kernel:1260631 org.kernel.vger.linux-pci:144578 org.kernel.vger.netdev:355153 Newsgroups: org.kernel.vger.linux-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-pci,org.kernel.vger.netdev Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail Hi, This series adds support for the LAN966x chip when used as a PCI device. For reference, the LAN996x chip is a System-on-chip that integrates an Ethernet switch and a number of other traditional hardware blocks such as a GPIO controller, I2C controllers, SPI controllers, etc. The LAN996x can be used in two different modes: - With Linux running on its Linux built-in ARM cores. This mode is already supported by the upstream Linux kernel, with the LAN996x described as a standard ARM Device Tree in arch/arm/boot/dts/microchip/lan966x.dtsi. Thanks to this support, all hardware blocks in the LAN996x already have drivers in the upstream Linux kernel. - As a PCI device, thanks to its built-in PCI endpoint controller. In this case, the LAN996x ARM cores are not used, but all peripherals of the LAN996x can be accessed by the PCI host using memory-mapped I/O through the PCI BARs. This series aims at supporting this second use-case. As all peripherals of the LAN996x already have drivers in the Linux kernel, our goal is to re-use them as-is to support this second use-case. Therefore, this patch series introduces a PCI driver that binds on the LAN996x PCI VID/PID, and when probed, instantiates all devices that are accessible through the PCI BAR. As the list and characteristics of such devices are non-discoverable, this PCI driver loads a Device Tree overlay that allows to teach the kernel about which devices are available, and allows to probe the relevant drivers in kernel, re-using all existing drivers with no change. This patch series for now adds a Device Tree overlay that describes an initial subset of the devices available over PCI in the LAN996x, and follow-up patch series will add support for more once this initial support has landed. In order to add this PCI driver, a number of preparation changes are needed: - Patches 1 to 5 allow the reset driver used for the LAN996x to be built as a module. Indeed, in the case where Linux runs on the ARM cores, it is common to have the reset driver built-in. However, when the LAN996x is used as a PCI device, it makes sense that all its drivers can be loaded as modules. - Patches 6 and 7 introduce the LAN996x PCI driver itself, together with its DT bindings. We believe all items from the above list can be merged separately, with no build dependencies. We expect: - Patches 1 to 5 to be taken by reset maintainers - Patch 6 and 7 by the MFD maintainers Additionally, we also believe all preparation items in this patch series can be taken even before there's a final agreement on the last part of the series (the MFD driver itself). [1] https://lore.kernel.org/all/CAL_Jsq+je7+9ATR=B6jXHjEJHjn24vQFs4Tvi9=vhDeK9n42Aw@mail.gmail.com/ Compare to the previous iteration: https://lore.kernel.org/lkml/20240614173232.1184015-1-herve.codina@bootlin.com/ this v3 series mainly: - Suppress patches as they were applied or extracted and handled in dedicated series. - Update the LAN966x PCI device driver. Best regards, Hervé Changes v2 -> v3 - Patches 1 and 5 No changes - Patch 6 (v2 patch 18) Add a blank line in the commit log to split paragraphs Remove unneeded header file inclusion Use IRQ_RETVAL() Remove blank line Use dev_of_node() Use pci_{set,get}_drvdata() Remove unneeded pci_clear_master() call Move { 0, } to { } Remove the unneeded pci_dev member from the lan966x_pci structure Use PCI_VENDOR_ID_EFAR instead of the hardcoded 0x1055 PCI Vendor ID Add a comment related to the of_node check. - Patch 7 (v2 patch 19) No changes Patches removed in v3 - Patches 6 and 7 Extracted and sent separately https://lore.kernel.org/lkml/20240620120126.412323-1-herve.codina@bootlin.com/ - Patches 9 Already applied - Patches 8, 10 to 12 Extracted, reworked and sent separately https://lore.kernel.org/lkml/20240614173232.1184015-1-herve.codina@bootlin.com/ - Patches 13 to 14 Already applied Changes v1 -> v2 - Patch 1 Fix a typo in syscon.h (s/intline/inline/) - Patches 2..5 No changes - Patch 6 Improve the reset property description - Patch 7 Fix a wrong reverse x-mass tree declaration - Patch 8 removed (sent alone to net) https://lore.kernel.org/lkml/20240513111853.58668-1-herve.codina@bootlin.com/ - Patch 8 (v1 patch 9) Add 'Reviewed-by: Rob Herring (Arm) ' - Patch 9 (v1 patch 10) Rephrase and ident parameters descriptions - Patch 10 (v1 patch 11) No changes - Patch 11 (v1 patch 12) Fix a missing ret value assignment before a goto in .probe() Limit lines to 80 columns Use indices in register offset definitions - Patch 13 and 14 (new patches in v2) Add new test cases for existing of_changeset_add_prop_*() - Patch 15 (v1 patch 14) No changes - Patch 16 (new patches in v2) Add tests for of_changeset_add_prop_bool() - Patch 17 (v1 patch 15) Update commit subject Rewrap a paragraph in commit log - Patch 18 (v1 patch 16) Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY - Patch 19 (v1 patch 17) No changes Clément Léger (5): mfd: syscon: Add reference counting and device managed support reset: mchp: sparx5: Remove dependencies and allow building as a module reset: mchp: sparx5: Release syscon when not use anymore reset: core: add get_device()/put_device on rcdev reset: mchp: sparx5: set the dev member of the reset controller Herve Codina (2): mfd: Add support for LAN966x PCI device MAINTAINERS: Add the Microchip LAN966x PCI driver entry MAINTAINERS | 6 + drivers/mfd/Kconfig | 24 +++ drivers/mfd/Makefile | 4 + drivers/mfd/lan966x_pci.c | 229 +++++++++++++++++++++++++ drivers/mfd/lan966x_pci.dtso | 167 ++++++++++++++++++ drivers/mfd/syscon.c | 145 +++++++++++++++- drivers/pci/quirks.c | 1 + drivers/reset/Kconfig | 3 +- drivers/reset/core.c | 2 + drivers/reset/reset-microchip-sparx5.c | 11 +- include/linux/mfd/syscon.h | 18 ++ 11 files changed, 593 insertions(+), 17 deletions(-) create mode 100644 drivers/mfd/lan966x_pci.c create mode 100644 drivers/mfd/lan966x_pci.dtso -- 2.45.0 . From: Sumit Saxena To: martin.petersen@oracle.com, helgaas@kernel.org, sathya.prakash@broadcom.com, sumit.saxena@broadcom.com, chandrakanth.patil@broadcom.com, ranjan.kumar@broadcom.com, prayas.patel@broadcom.com Cc: linux-scsi@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v5 0/3] mpi3mr: Support PCI Error Recovery Date: Thu, 27 Jun 2024 15:47:32 +0530 Message-Id: <20240627101735.18286-1-sumit.saxena@broadcom.com> X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000026a24e061bdc7c3d" Xref: photonic.trudheim.com org.kernel.vger.linux-pci:144589 Newsgroups: org.kernel.vger.linux-pci,org.kernel.vger.linux-scsi Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail --00000000000026a24e061bdc7c3d Content-Transfer-Encoding: 8bit This patch series contains the changes done in the driver to support PCI error recovery. It is rework of older patch series from Ranjan Kumar, see [1]. [1] https://lore.kernel.org/all/20231214205900.270488-1-ranjan.kumar@broadcom.com/ v1->v2: - AER patch split as suggested by Bjorn Helgaas. - Updated driver version to a new value. v2->v3: - Addressed the feedback from Bjorn Helgaas. - Simplified and dropped few patches. v3->v4: - Addressed the feedback from Bjorn Helgaas about dropping null pointer checks for shost and mrioc. v3->v5: - Replace sprintf with sysfs_emit and simplification in adp_state_show(). Sumit Saxena (3): mpi3mr: Support PCI Error Recovery callback handlers mpi3mr: Prevent PCI writes from driver during PCI error recovery mpi3mr: driver version update drivers/scsi/mpi3mr/mpi3mr.h | 11 +- drivers/scsi/mpi3mr/mpi3mr_app.c | 10 +- drivers/scsi/mpi3mr/mpi3mr_fw.c | 22 ++- drivers/scsi/mpi3mr/mpi3mr_os.c | 248 ++++++++++++++++++++++++- drivers/scsi/mpi3mr/mpi3mr_transport.c | 39 +++- 5 files changed, 311 insertions(+), 19 deletions(-) -- 2.31.1 --00000000000026a24e061bdc7c3d Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQbQYJKoZIhvcNAQcCoIIQXjCCEFoCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg3EMIIFDTCCA/WgAwIBAgIQeEqpED+lv77edQixNJMdADANBgkqhkiG9w0BAQsFADBMMSAwHgYD VQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UE AxMKR2xvYmFsU2lnbjAeFw0yMDA5MTYwMDAwMDBaFw0yODA5MTYwMDAwMDBaMFsxCzAJBgNVBAYT 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Message-ID: <7c5b8986-c69f-4ff5-9ed2-b2055ae848c4@siemens.com> Date: Thu, 27 Jun 2024 15:35:28 +0200 From: Jan Kiszka Subject: [PATCH v3] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Content-Language: en-US To: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Siddharth Vadapalli , Vignesh Raghavendra , Nishanth Menon , "linux-pci@vger.kernel.org" , Linux Kernel Mailing List , linux-arm-kernel Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xref: photonic.trudheim.com org.kernel.vger.linux-kernel:1260901 org.kernel.vger.linux-pci:144596 Newsgroups: org.kernel.vger.linux-kernel,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-pci Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail From: Kishon Vijay Abraham I Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 Bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Achal Verma Signed-off-by: Vignesh Raghavendra Signed-off-by: Jan Kiszka --- Original patch: Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ --- drivers/pci/controller/dwc/pci-keystone.c | 44 ++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..df9df2dc1f8a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -34,6 +34,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -104,6 +109,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -525,7 +532,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, @@ -537,6 +548,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -558,10 +574,36 @@ static void ks_pcie_quirk(struct pci_dev *dev) */ if (pci_match_id(rc_pci_devids, bridge)) { if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); + dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 Bytes. Force the MRRS to + * 128 Bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -- 2.43.0 .