Message-ID: Date: Fri, 28 Jun 2024 08:14:41 +0200 From: Jan Kiszka Subject: [PATCH v4] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Content-Language: en-US To: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Siddharth Vadapalli , Vignesh Raghavendra , Nishanth Menon , "linux-pci@vger.kernel.org" , Linux Kernel Mailing List , linux-arm-kernel Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xref: photonic.trudheim.com org.kernel.vger.linux-kernel:1261763 org.kernel.vger.linux-pci:144615 Newsgroups: org.kernel.vger.linux-kernel,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-pci Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail From: Kishon Vijay Abraham I Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Achal Verma Signed-off-by: Vignesh Raghavendra Signed-off-by: Jan Kiszka --- Original patch: Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ --- drivers/pci/controller/dwc/pci-keystone.c | 44 ++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..25e365c0c5c7 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -34,6 +34,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -104,6 +109,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -525,7 +532,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, @@ -537,6 +548,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -558,10 +574,36 @@ static void ks_pcie_quirk(struct pci_dev *dev) */ if (pci_match_id(rc_pci_devids, bridge)) { if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); + dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 bytes. Force the MRRS to + * 128 bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -- 2.43.0 . Message-ID: <16e1fcae-1ea7-46be-b157-096e05661b15@siemens.com> Date: Fri, 28 Jun 2024 13:45:29 +0200 From: Jan Kiszka Subject: [PATCH v5] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Content-Language: en-US To: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Siddharth Vadapalli , Vignesh Raghavendra , Nishanth Menon , "linux-pci@vger.kernel.org" , Linux Kernel Mailing List , linux-arm-kernel Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xref: photonic.trudheim.com org.kernel.vger.linux-kernel:1262099 org.kernel.vger.linux-pci:144619 Newsgroups: org.kernel.vger.linux-kernel,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-pci Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail From: Kishon Vijay Abraham I Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0 (SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an inbound PCIe TLP spans more than two internal AXI 128-byte bursts, the bus may corrupt the packet payload and the corrupt data may cause associated applications or the processor to hang. The workaround for Errata #i2037 is to limit the maximum read request size and maximum payload size to 128 bytes. Add workaround for Errata #i2037 here. The errata and workaround is applicable only to AM65x SR 1.0 and later versions of the silicon will have this fixed. [1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Achal Verma Signed-off-by: Vignesh Raghavendra Signed-off-by: Jan Kiszka Reviewed-by: Siddharth Vadapalli --- Original patch: Link: https://lore.kernel.org/linux-pci/20210325090026.8843-7-kishon@ti.com/ --- drivers/pci/controller/dwc/pci-keystone.c | 44 ++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d3a7d14ee685..25e365c0c5c7 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -34,6 +34,11 @@ #define PCIE_DEVICEID_SHIFT 16 /* Application registers */ +#define PID 0x000 +#define RTL GENMASK(15, 11) +#define RTL_SHIFT 11 +#define AM6_PCI_PG1_RTL_VER 0x15 + #define CMD_STATUS 0x004 #define LTSSM_EN_VAL BIT(0) #define OB_XLAT_EN_VAL BIT(1) @@ -104,6 +109,8 @@ #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +#define PCI_DEVICE_ID_TI_AM654X 0xb00c + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -525,7 +532,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci) static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; + struct keystone_pcie *ks_pcie; + struct device *bridge_dev; struct pci_dev *bridge; + u32 val; + static const struct pci_device_id rc_pci_devids[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK), .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, @@ -537,6 +548,11 @@ static void ks_pcie_quirk(struct pci_dev *dev) .class = PCI_CLASS_BRIDGE_PCI_NORMAL, .class_mask = ~0, }, { 0, }, }; + static const struct pci_device_id am6_pci_devids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; if (pci_is_root_bus(bus)) bridge = dev; @@ -558,10 +574,36 @@ static void ks_pcie_quirk(struct pci_dev *dev) */ if (pci_match_id(rc_pci_devids, bridge)) { if (pcie_get_readrq(dev) > 256) { - dev_info(&dev->dev, "limiting MRRS to 256\n"); + dev_info(&dev->dev, "limiting MRRS to 256 bytes\n"); pcie_set_readrq(dev, 256); } } + + /* + * Memory transactions fail with PCI controller in AM654 PG1.0 + * when MRRS is set to more than 128 bytes. Force the MRRS to + * 128 bytes in all downstream devices. + */ + if (pci_match_id(am6_pci_devids, bridge)) { + bridge_dev = pci_get_host_bridge_device(dev); + if (!bridge_dev && !bridge_dev->parent) + return; + + ks_pcie = dev_get_drvdata(bridge_dev->parent); + if (!ks_pcie) + return; + + val = ks_pcie_app_readl(ks_pcie, PID); + val &= RTL; + val >>= RTL_SHIFT; + if (val != AM6_PCI_PG1_RTL_VER) + return; + + if (pcie_get_readrq(dev) > 128) { + dev_info(&dev->dev, "limiting MRRS to 128 bytes\n"); + pcie_set_readrq(dev, 128); + } + } } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -- 2.43.0 . From: To: , CC: , , , , , , , , , , Subject: [PATCH v6 0/3] Fix address translations on MPFS PCIe controller Date: Fri, 28 Jun 2024 12:59:20 +0100 Message-ID: <20240628115923.4133286-1-daire.mcnamara@microchip.com> X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Xref: photonic.trudheim.com org.kernel.vger.linux-pci:144620 org.infradead.lists.linux-riscv:79179 org.kernel.vger.linux-kernel:1262107 Newsgroups: org.kernel.vger.linux-pci,org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail From: Daire McNamara Hi all, On Microchip PolarFire SoC (MPFS), the PCIe controller is connected to the CPU via one of three Fabric Interface Connectors (FICs). Each FIC present to the CPU complex as 64-bit AXI-M and 64-bit AXI-S. To preserve compatibility with other PolarFire family members, the PCIe controller is connected to its encapsulating FIC via a 32-bit AXI-M and 32-bit AXI-S interface. Each FIC is implemented in FPGA logic and can incorporate logic along its 64-bit AXI-M to 32-bit AXI-M chain (including address translation) and, likewise, along its 32-bit AXI-S to 64-bit AXI-S chain (again including address translation). In order to reduce the potential support space for the PCIe controller in this environment, MPFS supports certain reference designs for these address translations: reference designs for cache-coherent memory accesses and reference designs for non-cache-coherent memory accesses. The precise details of these reference designs and associated customer guidelines recommending that customers adhere to the addressing schemes used in those reference designs are available from Microchip, but the implication for the PCIe controller address translation between CPU-space and PCIe-space are: For outbound address translation, the PCIe controller address translation tables are treated as if they are 32-bit only. Any further address translation must be done in FPGA fabric. For inbound address translation, the PCIe controller is configurable for two cases: * In the case of cache-coherent designs, the base of the AXI-S side of the address translation must be set to 0 and the size should be 4 GiB wide. The FPGA fabric must complete any address translations based on that 0-based address translation. * In the case of non-cache coherent designs, the base of AXI-S side of the address translation must be set to 0x8000'0000 and the size shall be 2 GiB wide. The FPGA fabric must complete any address translation based on that 0x80000000 base. So, for example, in the non-cache-coherent case, with a device tree property that maps an inbound range from 0x10'0000'0000 in PCIe space to 0x10'0000'0000 in CPU space, the PCIe rootport will translate a PCIe address of 0x10'0000'0000 to an intermediate 32-bit AXI-S address of 0x8000'0000 and the FIC is responsible for translating that intermediate 32-bit AXI-S address of 0x8000'0000 to a 64-bit AXI-S address of 0x10'0000'0000. And similarly, for example, in the cache-coherent case, with a device tree property that maps an inbound range from 0x10'0000'0000 in PCIe space to 0x10'0000'0000 in CPU space, the PCIe rootport will translate a PCIe address of 0x10'0000'0000 to an intermediate 32-bit AXI-S address of 0x0000'0000 and the FIC is responsible for translating that intermediate 32-bit AXI-S address of 0x0000'0000 to a 64-bit AXI-S address of 0x10'0000'0000. See https://lore.kernel.org/all/20220902142202.2437658-1-daire.mcnamara@microchip.com/T/ for backstory. Changes since v5: - Reverted setup_inbound_atr size parameter to u64 as ci system reported SZ_4G getting truncated to 0 on mips when I try to use size_t or resource_size_t. Added Acked-by tags Changes since v4: - Added more cleanups suggested by Ilpo Jarvinen Added cleanups for inbound v4 and outbound v3. Changes since v3: - Added nice cleanups suggested by Ilpo Jarvinen Changes since v2: - Added Changes since v1: - added bindings patch to allow dma-noncoherent - changed a size_t to u64 to pass 32-bit compile tests - allowed 64-bit outbound pcie translations - tied PCIe side of eCAM translation table to 0 Conor Dooley (1): dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent Daire McNamara (2): PCI: microchip: Fix outbound address translation tables PCI: microchip: Fix inbound address translation tables .../bindings/pci/microchip,pcie-host.yaml | 2 + drivers/pci/controller/pcie-microchip-host.c | 118 +++++++++++++++--- 2 files changed, 106 insertions(+), 14 deletions(-) base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6 -- 2.34.1 . From: Frank Li To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Cc: imx@lists.linux.dev Subject: [PATCH 1/1] dt-bindings: PCI: layerscape-pci: Fix property 'fsl,pcie-scfg' type Date: Fri, 28 Jun 2024 10:48:57 -0400 Message-Id: <20240628144858.2363300-1-Frank.Li@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Xref: photonic.trudheim.com org.kernel.vger.linux-kernel:1262294 org.kernel.vger.linux-pci:144624 Newsgroups: org.kernel.vger.linux-kernel,dev.linux.lists.imx,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-pci Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail fsl,pcie-scfg actually need an argument when there are more than one PCIe instances. Change it to phandle-array and use items to describe each field means. Fix below warning. arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: pcie@3400000: fsl,pcie-scfg:0: [22, 0] is too long from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# Signed-off-by: Frank Li --- Change from v1 to v2 - update commit message. --- .../devicetree/bindings/pci/fsl,layerscape-pcie.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml index 793986c5af7ff..679c2989de7a2 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -43,10 +43,16 @@ properties: - const: config fsl,pcie-scfg: - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array description: A phandle to the SCFG device node. The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers. + items: + items: + - description: A phandle to the SCFG device node + - description: PCIe controller index starting from '0' + minItems: 1 + maxItems: 1 big-endian: $ref: /schemas/types.yaml#/definitions/flag -- 2.34.1 . Date: Sat, 29 Jun 2024 00:31:57 +0800 From: kernel test robot To: "Krzysztof =?utf-8?Q?Wilczy=C5=84ski"?= Cc: linux-pci@vger.kernel.org Subject: [pci:controller/layerscape] BUILD SUCCESS cd09a6ac85b9f7ee9ee249c2feede223bf97dbc4 Message-ID: <202406290055.qxflDhNs-lkp@intel.com> X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Xref: photonic.trudheim.com org.kernel.vger.linux-pci:144625 Newsgroups: org.kernel.vger.linux-pci Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git controller/layerscape branch HEAD: cd09a6ac85b9f7ee9ee249c2feede223bf97dbc4 PCI: ls-gen4: Make struct mobiveil_rp_ops constant elapsed time: 5210m configs tested: 170 configs skipped: 2 The following configs have been built successfully. More configs may be tested in the coming days. tested configs: alpha allnoconfig gcc-13.2.0 alpha defconfig gcc-13.2.0 arc allmodconfig gcc-13.2.0 arc allnoconfig gcc-13.2.0 arc allyesconfig gcc-13.2.0 arc defconfig gcc-13.2.0 arc randconfig-001-20240628 gcc-13.2.0 arc randconfig-002-20240628 gcc-13.2.0 arm allmodconfig gcc-13.2.0 arm allnoconfig gcc-13.2.0 arm allyesconfig gcc-13.2.0 arm am200epdkit_defconfig gcc-13.2.0 arm bcm2835_defconfig gcc-13.2.0 arm davinci_all_defconfig gcc-13.2.0 arm defconfig gcc-13.2.0 arm multi_v5_defconfig gcc-13.2.0 arm mv78xx0_defconfig gcc-13.2.0 arm mvebu_v7_defconfig gcc-13.2.0 arm omap1_defconfig gcc-13.2.0 arm randconfig-001-20240628 gcc-13.2.0 arm randconfig-002-20240628 gcc-13.2.0 arm randconfig-003-20240628 gcc-13.2.0 arm randconfig-004-20240628 gcc-13.2.0 arm tegra_defconfig gcc-13.2.0 arm64 allmodconfig gcc-13.2.0 arm64 allnoconfig gcc-13.2.0 arm64 allyesconfig clang-19 arm64 defconfig gcc-13.2.0 arm64 randconfig-001-20240628 gcc-13.2.0 arm64 randconfig-002-20240628 gcc-13.2.0 arm64 randconfig-003-20240628 gcc-13.2.0 arm64 randconfig-004-20240628 gcc-13.2.0 csky allnoconfig gcc-13.2.0 csky defconfig gcc-13.2.0 csky randconfig-001-20240628 gcc-13.2.0 csky randconfig-002-20240628 gcc-13.2.0 i386 allmodconfig clang-18 i386 allnoconfig clang-18 i386 allyesconfig clang-18 i386 buildonly-randconfig-001-20240628 gcc-10 i386 buildonly-randconfig-002-20240628 gcc-10 i386 buildonly-randconfig-003-20240628 gcc-10 i386 buildonly-randconfig-004-20240628 gcc-10 i386 buildonly-randconfig-005-20240628 gcc-10 i386 buildonly-randconfig-006-20240628 gcc-10 i386 defconfig clang-18 i386 randconfig-001-20240628 gcc-10 i386 randconfig-002-20240628 gcc-10 i386 randconfig-003-20240628 gcc-10 i386 randconfig-004-20240628 gcc-10 i386 randconfig-005-20240628 gcc-10 i386 randconfig-006-20240628 gcc-10 i386 randconfig-011-20240628 gcc-10 i386 randconfig-012-20240628 gcc-10 i386 randconfig-013-20240628 gcc-10 i386 randconfig-014-20240628 gcc-10 i386 randconfig-015-20240628 gcc-10 i386 randconfig-016-20240628 gcc-10 loongarch allmodconfig gcc-13.2.0 loongarch allnoconfig gcc-13.2.0 loongarch defconfig gcc-13.2.0 loongarch randconfig-001-20240628 gcc-13.2.0 loongarch randconfig-002-20240628 gcc-13.2.0 m68k allmodconfig gcc-13.2.0 m68k allnoconfig gcc-13.2.0 m68k allyesconfig gcc-13.2.0 m68k defconfig gcc-13.2.0 microblaze allmodconfig gcc-13.2.0 microblaze allnoconfig gcc-13.2.0 microblaze allyesconfig gcc-13.2.0 microblaze defconfig gcc-13.2.0 mips allmodconfig clang-19 mips allnoconfig gcc-13.2.0 mips allyesconfig clang-19 mips ath79_defconfig gcc-13.2.0 mips qi_lb60_defconfig gcc-13.2.0 nios2 allmodconfig gcc-13.2.0 nios2 allnoconfig gcc-13.2.0 nios2 allyesconfig gcc-13.2.0 nios2 defconfig gcc-13.2.0 nios2 randconfig-001-20240628 gcc-13.2.0 nios2 randconfig-002-20240628 gcc-13.2.0 openrisc allmodconfig gcc-13.2.0 openrisc allnoconfig gcc-13.2.0 openrisc allyesconfig gcc-13.2.0 openrisc defconfig gcc-13.2.0 parisc allmodconfig gcc-13.2.0 parisc allnoconfig gcc-13.2.0 parisc allyesconfig gcc-13.2.0 parisc defconfig gcc-13.2.0 parisc randconfig-001-20240628 gcc-13.2.0 parisc randconfig-002-20240628 gcc-13.2.0 parisc64 defconfig gcc-13.2.0 powerpc allmodconfig gcc-13.2.0 powerpc allnoconfig gcc-13.2.0 powerpc allyesconfig gcc-13.2.0 powerpc amigaone_defconfig gcc-13.2.0 powerpc klondike_defconfig gcc-13.2.0 powerpc mvme5100_defconfig gcc-13.2.0 powerpc ppc44x_defconfig gcc-13.2.0 powerpc randconfig-001-20240628 gcc-13.2.0 powerpc randconfig-002-20240628 gcc-13.2.0 powerpc randconfig-003-20240628 gcc-13.2.0 powerpc64 randconfig-001-20240628 gcc-13.2.0 powerpc64 randconfig-002-20240628 gcc-13.2.0 powerpc64 randconfig-003-20240628 gcc-13.2.0 riscv allmodconfig gcc-13.2.0 riscv allnoconfig gcc-13.2.0 riscv allyesconfig gcc-13.2.0 riscv defconfig gcc-13.2.0 riscv randconfig-001-20240628 gcc-13.2.0 riscv randconfig-002-20240628 gcc-13.2.0 s390 allnoconfig gcc-13.2.0 s390 defconfig gcc-13.2.0 s390 randconfig-001-20240628 gcc-13.2.0 s390 randconfig-002-20240628 gcc-13.2.0 sh allnoconfig gcc-13.2.0 sh defconfig gcc-13.2.0 sh lboxre2_defconfig gcc-13.2.0 sh randconfig-001-20240628 gcc-13.2.0 sh randconfig-002-20240628 gcc-13.2.0 sh rsk7264_defconfig gcc-13.2.0 sh sh7785lcr_defconfig gcc-13.2.0 sparc allyesconfig gcc-13.2.0 sparc64 allmodconfig gcc-13.2.0 sparc64 allyesconfig gcc-13.2.0 sparc64 defconfig gcc-13.2.0 sparc64 randconfig-001-20240628 gcc-13.2.0 sparc64 randconfig-002-20240628 gcc-13.2.0 um allnoconfig gcc-13.2.0 um defconfig gcc-13.2.0 um i386_defconfig gcc-13.2.0 um randconfig-001-20240628 gcc-13.2.0 um randconfig-002-20240628 gcc-13.2.0 um x86_64_defconfig gcc-13.2.0 x86_64 allnoconfig clang-18 x86_64 allyesconfig clang-18 x86_64 buildonly-randconfig-001-20240628 gcc-13 x86_64 buildonly-randconfig-002-20240628 gcc-13 x86_64 buildonly-randconfig-003-20240628 gcc-13 x86_64 buildonly-randconfig-004-20240628 gcc-13 x86_64 buildonly-randconfig-005-20240628 gcc-13 x86_64 buildonly-randconfig-006-20240628 gcc-13 x86_64 defconfig clang-18 x86_64 kexec clang-18 x86_64 randconfig-001-20240628 gcc-13 x86_64 randconfig-002-20240628 gcc-13 x86_64 randconfig-003-20240628 gcc-13 x86_64 randconfig-004-20240628 gcc-13 x86_64 randconfig-005-20240628 gcc-13 x86_64 randconfig-006-20240628 gcc-13 x86_64 randconfig-011-20240628 gcc-13 x86_64 randconfig-012-20240628 gcc-13 x86_64 randconfig-013-20240628 gcc-13 x86_64 randconfig-014-20240628 gcc-13 x86_64 randconfig-015-20240628 gcc-13 x86_64 randconfig-016-20240628 gcc-13 x86_64 randconfig-071-20240628 gcc-13 x86_64 randconfig-072-20240628 gcc-13 x86_64 randconfig-073-20240628 gcc-13 x86_64 randconfig-074-20240628 gcc-13 x86_64 randconfig-075-20240628 gcc-13 x86_64 randconfig-076-20240628 gcc-13 x86_64 rhel-8.3-func clang-18 x86_64 rhel-8.3-rust clang-18 x86_64 rhel-8.3 clang-18 xtensa allnoconfig gcc-13.2.0 xtensa allyesconfig gcc-13.2.0 xtensa randconfig-001-20240628 gcc-13.2.0 xtensa randconfig-002-20240628 gcc-13.2.0 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki . From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), Rob Herring Subject: [PATCH v1 0/8] PCI: brcnstb: Enable STB 7712 SOC Date: Fri, 28 Jun 2024 16:54:19 -0400 Message-Id: <20240628205430.24775-1-james.quinlan@broadcom.com> Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="0000000000008530b9061bf97495" X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Xref: photonic.trudheim.com org.kernel.vger.linux-kernel:1262670 org.kernel.vger.linux-pci:144632 Newsgroups: org.kernel.vger.linux-kernel,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-pci Path: photonic.trudheim.com!nntp.lore.kernel.org!not-for-mail --0000000000008530b9061bf97495 This submission is for the Broadcom STB 7712, sibling SOC of the RPi5 chip. Stanimir has already submitted a patch "Add PCIe support for bcm2712" for the RPi version of the SOC. It is hoped that Stanimir will allow us to submit this series first and subsequently rebase his patch(es). The largest commit, "Refactor for chips with many regular inbound BARs" affects both the STB and RPi SOCs. It allows for multiple inbound ranges where previously only one was effectively used. This feature will also be present in future STB chips, as well as Broadcom's Cable Modem group. Jim Quinlan (8): dt-bindings: PCI: Add Broadcom STB 7712 SOC, update maintainter PCI: brcmstb: Use "clk_out" error path label PCI: brcmstb: Use bridge reset if available PCI: brcmstb: Use swinit reset if available PCI: brcmstb: Two more register offsets vary by SOC PCI: brcmstb: Don't conflate the reset rescal with phy ctrl PCI: brcmstb: Refactor for chips with many regular inbound BARs PCI: brcmstb: Enable 7712 SOCs .../bindings/pci/brcm,stb-pcie.yaml | 24 +- drivers/pci/controller/pcie-brcmstb.c | 330 ++++++++++++++---- 2 files changed, 276 insertions(+), 78 deletions(-) base-commit: 55027e689933ba2e64f3d245fb1ff185b3e7fc81 -- 2.17.1 --0000000000008530b9061bf97495 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQbgYJKoZIhvcNAQcCoIIQXzCCEFsCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg 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