Subject: [PATCH v2 0/5] Consolidate lan9118 phy implementations From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Jason Wang , qemu-arm@nongnu.org, Peter Maydell , Guenter Roeck , Paolo Bonzini , Bernhard Beschow Date: Wed, 16 Oct 2024 23:24:02 +0200 . Subject: [PATCH v4 00/19] s390x: Add Full Boot Order Support From: jrossi@linux.ibm.com To: qemu-devel@nongnu.org, qemu-s390x@nongnu.org, thuth@redhat.com Cc: frankja@linux.ibm.com, jrossi@linux.ibm.com Date: Wed, 16 Oct 2024 21:47:29 -0400 . Subject: [PATCH v2 0/2] linux-headers: loongarch: Add kvm_para.h and unistd_64.h From: Bibo Mao To: "Michael S . Tsirkin" Cc: Cornelia Huck , Paolo Bonzini , qemu-devel@nongnu.org, Song Gao Date: Thu, 17 Oct 2024 10:07:06 +0800 . Subject: How to use "subprojects/slirp.wrap"? From: Liu Jaloo To: qemu-devel@nongnu.org Date: Thu, 17 Oct 2024 10:08:53 +0800 . Subject: Re: [PATCH 10/16] rust: introduce alternative implementation of offset_of! From: Junjie Mao To: Paolo Bonzini Cc: qemu-devel@nongnu.org Date: Thu, 17 Oct 2024 13:07:46 +0800 . Subject: [PATCH v4 0/6] migration: auto-converge refinements for huge VM From: yong.huang@smartx.com To: qemu-devel@nongnu.org Cc: Peter Xu , Fabiano Rosas , Richard Henderson , Paolo Bonzini , yong.huang@smartx.com Date: Thu, 17 Oct 2024 14:42:49 +0800 . Subject: [PATCH] crypto/hash-afalg: Fix broken build From: Markus Armbruster To: qemu-devel@nongnu.org Cc: berrange@redhat.com, clg@redhat.com, alejandro.zeise@seagate.com, peter.maydell@linaro.org Date: Thu, 17 Oct 2024 08:47:42 +0200 . Subject: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board From: Sai Pavan Boddu To: , Date: Thu, 17 Oct 2024 12:55:07 +0530 . Subject: [PATCH] tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 17 Oct 2024 11:14:01 +0200 . Subject: [PATCH] linux-user: Trace rt_sigprocmask's sigsets From: Ilya Leoshkevich To: Laurent Vivier , Richard Henderson Cc: qemu-devel@nongnu.org, Ilya Leoshkevich Date: Thu, 17 Oct 2024 11:14:37 +0200 . Subject: [PATCH] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 From: Amit Machhiwal To: Nicholas Piggin , qemu-ppc@nongnu.org, Vaibhav Jain , Harsh Prateek Bora Cc: David Gibson , Daniel Henrique Barboza , qemu-devel@nongnu.org, Amit Machhiwal Date: Thu, 17 Oct 2024 16:30:33 +0530 . Subject: [PATCH v2 00/31] include: move include/qapi/qmp/ to include/qobject/ From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= To: qemu-devel@nongnu.org Cc: Markus Armbruster , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Date: Thu, 17 Oct 2024 12:33:12 +0100 . Subject: [PATCH] pcie: enable Extended tag field capability From: Marcin Juszkiewicz To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Marcel Apfelbaum , Marcin Juszkiewicz Date: Thu, 17 Oct 2024 15:33:44 +0200 . Subject: [PATCH 0/2] linux-user/ppc: Fix sigmask endianness issue in sigreturn From: Ilya Leoshkevich To: Laurent Vivier , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Cc: qemu-devel@nongnu.org, Ilya Leoshkevich Date: Thu, 17 Oct 2024 14:54:42 +0200 . Subject: [RFC 0/2] rust/qemu-api: Rethink property definition macro From: Zhao Liu To: Manos Pitsidianakis , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Junjie Mao , Zhao Liu Date: Thu, 17 Oct 2024 22:32:43 +0800 . Subject: [PATCH 0/4] tests/qtest: Move the bulk of migration tests into a separate target From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: Peter Xu , Peter Maydell Date: Thu, 17 Oct 2024 11:32:07 -0300 . Subject: [PATCH v5 0/8] chardev: implement backend chardev multiplexing From: Roman Penyaev To: Cc: Roman Penyaev , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-devel@nongnu.org Date: Thu, 17 Oct 2024 16:43:08 +0200 . Subject: [PATCH v4 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Date: Thu, 17 Oct 2024 16:52:11 +0200 . Subject: [RFC V1 00/14] precreate phase From: Steve Sistare To: qemu-devel@nongnu.org Cc: Peter Xu , Fabiano Rosas , David Hildenbrand , Marcel Apfelbaum , Eduardo Habkost , Philippe Mathieu-Daude , Paolo Bonzini , "Daniel P. Berrange" , Markus Armbruster , Steve Sistare Date: Thu, 17 Oct 2024 08:14:01 -0700 . Subject: [PATCH v2 0/2] Fix for multi-process gdbstub breakpoints From: Roque Arcudia Hernandez To: richard.henderson@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, philmd@linaro.org, slongfield@google.com, komlodi@google.com Cc: qemu-devel@nongnu.org, Roque Arcudia Hernandez Date: Thu, 17 Oct 2024 08:37:43 -0700 . Subject: [PATCH] hw/sd/omap_mmc: Don't use sd_cmd_type_t From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Guenter Roeck Date: Thu, 17 Oct 2024 17:27:55 +0100 . Subject: [PATCH 0/2] arm: Add collie and sx functional tests From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Guenter Roeck , Thomas Huth Date: Thu, 17 Oct 2024 17:32:45 +0100 . Subject: [PATCH] target/arm: Don't assert in regime_is_user() for E10 mmuidx values From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org Date: Thu, 17 Oct 2024 18:23:31 +0100 . Subject: [PULL v2 00/26] x86 and KVM patches for 2024-10-15 From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org Date: Thu, 17 Oct 2024 19:44:08 +0200 The following changes since commit f774a677507966222624a9b2859f06ede7608100: Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/p= maydell/qemu-arm into staging (2024-10-15 15:18:22 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 15d955975bd484c2c66af0d6daaa02a7d04d2256: target/i386: Use only 16 and 32-bit operands for IN/OUT (2024-10-17 19:41= :30 +0200) ---------------------------------------------------------------- * tcg/s390x: Fix for TSTEQ/TSTNE * target/i386: Fixes for IN and OUT with REX prefix * target/i386: New CPUID features and logic fixes * target/i386: Add support save/load HWCR MSR * target/i386: Move more instructions to new decoder; separate decoding and IR generation * target/i386/tcg: Use DPL-level accesses for interrupts and call gates * accel/kvm: perform capability checks on VM file descriptor when necessary * accel/kvm: dynamically sized kvm memslots array * target/i386: fixes for Hyper-V * docs/system: Add recommendations to Hyper-V enlightenments doc ---------------------------------------------------------------- v1->v2: new patch to fix tcg/s390x mark new patch and "check for KVM_CAP_READONLY_MEM on VM" for stable Chao Gao (1): target/i386: Add more features enumerated by CPUID.7.2.EDX Gao Shiyuan (1): target/i386: Add support save/load HWCR MSR Paolo Bonzini (10): tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE target/i386: convert bit test instructions to new decoder target/i386: decode address before going back to translate.c target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder target/i386: do not check PREFIX_LOCK in old-style decoder target/i386: list instructions still in translate.c target/i386: assert that cc_op* and pc_save are preserved target/i386/tcg: Use DPL-level accesses for interrupts and call gates accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vm Peter Xu (4): KVM: Dynamic sized kvm memslots array KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used KVM: Rename KVMState->nr_slots to nr_slots_max Richard Henderson (1): target/i386: Use only 16 and 32-bit operands for IN/OUT Tom Dohrmann (1): accel/kvm: check for KVM_CAP_READONLY_MEM on VM Vitaly Kuznetsov (4): target/i386: Fix conditional CONFIG_SYNDBG enablement target/i386: Exclude 'hv-syndbg' from 'hv-passthrough' target/i386: Make sure SynIC state is really updated before KVM_RUN docs/system: Add recommendations to Hyper-V enlightenments doc Xiaoyao Li (4): target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f] target/i386: Enable fdp-excptn-only and zero-fcs-fds target/i386: Construct CPUID 2 as stateful iff times > 1 target/i386: Make invtsc migratable when user sets tsc-khz explicitly docs/system/i386/hyperv.rst | 43 +++- include/sysemu/kvm_int.h | 7 +- target/i386/cpu.h | 9 + target/i386/tcg/decode-new.h | 19 +- accel/kvm/kvm-all.c | 131 ++++++++---- target/i386/cpu.c | 21 +- target/i386/kvm/hyperv.c | 1 + target/i386/kvm/kvm.c | 47 +++-- target/i386/machine.c | 20 ++ target/i386/tcg/seg_helper.c | 17 +- target/i386/tcg/translate.c | 444 ++++++-----------------------------= ---- target/i386/tcg/decode-new.c.inc | 145 +++++++++---- target/i386/tcg/emit.c.inc | 246 +++++++++++++++++++++- tcg/s390x/tcg-target.c.inc | 24 ++- accel/kvm/trace-events | 1 + 15 files changed, 682 insertions(+), 493 deletions(-) --=20 2.46.2 From: Paolo Bonzini Date: Thu, 17 Oct 2024 11:09:52 +0200 Subject: [PULL 11/26] tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit 32-bit TSTEQ and TSTNE is subject to the same constraints as for 64-bit, but setcond_i32 and negsetcond_i32 were incorrectly using TCG_CT_CONST ("i") instead of TCG_CT_CONST_CMP ("C"). Adjust the constraint and make tcg_target_const_match use the same sequence as tgen_cmp2: first check if the constant is a valid operand for TSTEQ/TSTNE, then accept everything for 32-bit non-test comparisons, finally check if the constant is a valid operand for 64-bit non-test comparisons. Reported-by: Philippe Mathieu-Daud=C3=A9 Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini --- tcg/s390x/tcg-target.c.inc | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a5d57197a4b..27bccc14e50 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -565,6 +565,20 @@ static bool tcg_target_const_match(int64_t val, int ct, } =20 if (ct & TCG_CT_CONST_CMP) { + if (is_tst_cond(cond)) { + if (is_const_p16(uval) >=3D 0) { + return true; /* TMxx */ + } + if (risbg_mask(uval)) { + return true; /* RISBG */ + } + return false; + } + + if (type =3D=3D TCG_TYPE_I32) { + return true; + } + switch (cond) { case TCG_COND_EQ: case TCG_COND_NE: @@ -584,13 +598,7 @@ static bool tcg_target_const_match(int64_t val, int ct, break; case TCG_COND_TSTNE: case TCG_COND_TSTEQ: - if (is_const_p16(uval) >=3D 0) { - return true; /* TMxx */ - } - if (risbg_mask(uval)) { - return true; /* RISBG */ - } - break; + /* checked above, fallthru */ default: g_assert_not_reached(); } @@ -3231,9 +3239,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + return C_O1_I2(r, r, ri); case INDEX_op_setcond_i32: case INDEX_op_negsetcond_i32: - return C_O1_I2(r, r, ri); case INDEX_op_setcond_i64: case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rC); --=20 2.46.2 . Subject: Seeking your thoughts on LLM-generated contributions From: Daniel Pono Takamori To: qemu-devel@nongnu.org Date: Thu, 17 Oct 2024 14:14:48 -0700 . Subject: [PATCH 0/2] Allow injection of virtio-gpu EDID name From: Roque Arcudia Hernandez To: ankeesler@google.com, mst@redhat.com, marcandre.lureau@redhat.com Cc: qemu-devel@nongnu.org, venture@google.com, Roque Arcudia Hernandez Date: Thu, 17 Oct 2024 21:53:02 +0000 .