Date: Tue, 15 Oct 2024 12:51:42 +0400 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Subject: [PULL 0/8] Chr patches From: Marc-André Lureau The following changes since commit aa54f5be44be786636a5d51cc1612ad208a24849: tests: update lcitool to fix freebsd py311-yaml rename (2024-10-14 15:54:24 +0100) are available in the Git repository at: https://gitlab.com/marcandre.lureau/qemu.git tags/chr-pull-request for you to fetch changes up to 95806c7bee232e995ffd963a6fea0a34fbabc937: tests/unit/test-char: implement a few mux remove test cases (2024-10-15 12:48:53 +0400) ---------------------------------------------------------------- chardev patch queue ---------------------------------------------------------------- Roman Penyaev (8): chardev/char: fix qemu_chr_is_busy() check chardev/chardev-internal: remove unused `max_size` struct member chardev/mux: use bool type for `linestart` and `term_got_escape` chardev/mux: convert size members to unsigned int chardev/mux: introduce `mux_chr_attach_frontend() call chardev/mux: switch mux frontends management to bitset chardev/mux: implement detach of frontends from mux tests/unit/test-char: implement a few mux remove test cases chardev/chardev-internal.h | 16 ++++--- include/chardev/char-fe.h | 2 +- chardev/char-fe.c | 13 ++---- chardev/char-mux.c | 90 ++++++++++++++++++++++++++++---------- chardev/char.c | 2 +- tests/unit/test-char.c | 24 +++++++++- 6 files changed, 105 insertions(+), 42 deletions(-) -- 2.47.0 . Date: Tue, 15 Oct 2024 11:37:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 00/28] target-arm queue The following changes since commit 35152940b78e478b97051a799cb6275ced03192e: Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-10-14 17:05:25 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241015 for you to fetch changes up to 9bb9833fd2ef30c5c7306c6f2a15dcc313305ccc: hw/arm/xilinx_zynq: Add various missing unimplemented devices (2024-10-15 11:29:47 +0100) ---------------------------------------------------------------- target-arm queue: * hw/arm/omap1: Remove unused omap_uwire_attach() method * stm32f405: Add RCC device to stm32f405 SoC * arm/gicv3: add missing casts * hw/misc: Create STM32L4x5 SYSCFG clock * hw/arm: Add SPI to Allwinner A10 * hw/intc/omap_intc: Remove now-unnecessary abstract base class * hw/char/pl011: Use correct masks for IBRD and FBRD * docs/devel: Convert txt files to rST * Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only by now-removed omap/pxa2xx boards) * vl.c: Remove pxa2xx-specific -portrait and -rotate options * dma: Fix function names in documentation * hw/arm/xilinx_zynq: Add various missing unimplemented devices ---------------------------------------------------------------- Akihiko Odaki (1): dma: Fix function names in documentation Alexandra Diupina (3): hw/intc/arm_gicv3: Add cast to match the documentation hw/intc/arm_gicv3: Add cast to match the documentation hw/intc/arm_gicv3_cpuif: Add cast to match the documentation Chao Liu (1): hw/arm/xilinx_zynq: Add various missing unimplemented devices Inès Varhol (3): hw/misc: Create STM32L4x5 SYSCFG clock hw/clock: Expose 'qtest-clock-period' QOM property for QTests tests/qtest: Check STM32L4x5 clock connections Peter Maydell (15): hw/intc/omap_intc: Remove now-unnecessary abstract base class hw/char/pl011: Use correct masks for IBRD and FBRD docs/devel/blkdebug: Convert to rST format docs/devel/blkverify: Convert to rST format docs/devel/lockcnt: Convert to rST format docs/devel/multiple-iothreads: Convert to rST format docs/devel/rcu: Convert to rST format include: Move QemuLockCnt APIs to their own header docs/devel/lockcnt: Include kernel-doc API documentation hw/adc: Remove MAX111X device hw/gpio: Remove MAX7310 device hw/ide: Remove DSCM-1XXXX microdrive device model hw: Remove PCMCIA subsystem hw/block: Remove ecc vl.c: Remove pxa2xx-specific -portrait and -rotate options Philippe Mathieu-Daudé (1): hw/arm/omap1: Remove unused omap_uwire_attach() method Román Cárdenas Rodríguez (2): hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCs hw/arm/stm32f405: Add RCC device to stm32f405 SoC Strahinja Jankovic (2): hw/ssi: Allwinner A10 SPI emulation hw/arm: Add SPI to Allwinner A10 MAINTAINERS | 10 +- docs/about/removed-features.rst | 23 + docs/devel/blkdebug.txt | 162 ------ docs/devel/clocks.rst | 6 + docs/devel/index-api.rst | 1 + docs/devel/index-internals.rst | 2 + docs/devel/{lockcnt.txt => lockcnt.rst} | 89 +-- docs/devel/multiple-iothreads.rst | 139 +++++ docs/devel/multiple-iothreads.txt | 130 ----- docs/devel/{rcu.txt => rcu.rst} | 172 +++--- docs/devel/testing/blkdebug.rst | 177 ++++++ .../devel/{blkverify.txt => testing/blkverify.rst} | 30 +- docs/devel/testing/index.rst | 2 + docs/system/arm/cubieboard.rst | 1 + docs/system/arm/stm32.rst | 3 +- include/block/aio.h | 1 + include/hw/adc/max111x.h | 56 -- include/hw/arm/allwinner-a10.h | 2 + include/hw/arm/omap.h | 10 +- include/hw/arm/stm32f405_soc.h | 2 + include/hw/block/flash.h | 11 - include/hw/core/cpu.h | 1 + include/hw/misc/stm32_rcc.h | 91 +++ include/hw/misc/stm32l4x5_syscfg.h | 1 + include/hw/pcmcia.h | 66 --- include/hw/ssi/allwinner-a10-spi.h | 57 ++ include/qemu/lockcnt.h | 130 +++++ include/qemu/thread.h | 111 ---- include/sysemu/dma.h | 11 +- include/sysemu/sysemu.h | 1 - tests/qtest/stm32l4x5.h | 42 ++ accel/accel-blocker.c | 1 + hw/adc/max111x.c | 236 -------- hw/arm/allwinner-a10.c | 8 + hw/arm/omap1.c | 29 +- hw/arm/stm32f405_soc.c | 12 +- hw/arm/stm32l4x5_soc.c | 2 + hw/arm/xilinx_zynq.c | 70 +++ hw/block/ecc.c | 91 --- hw/char/pl011.c | 4 +- hw/core/clock.c | 16 + hw/core/cpu-common.c | 1 + hw/gpio/max7310.c | 217 ------- hw/ide/microdrive.c | 644 --------------------- hw/intc/arm_gicv3_cpuif.c | 6 +- hw/intc/omap_intc.c | 13 +- hw/misc/stm32_rcc.c | 162 ++++++ hw/misc/stm32l4x5_syscfg.c | 19 +- hw/pcmcia/pcmcia.c | 24 - hw/ssi/allwinner-a10-spi.c | 561 ++++++++++++++++++ system/globals.c | 1 - system/vl.c | 11 - tests/qtest/stm32l4x5_gpio-test.c | 23 + tests/qtest/stm32l4x5_syscfg-test.c | 20 +- tests/qtest/stm32l4x5_usart-test.c | 26 + ui/input.c | 36 -- util/aio-posix.c | 1 + util/aio-win32.c | 1 + util/async.c | 1 + util/fdmon-epoll.c | 1 + util/lockcnt.c | 1 + hw/Kconfig | 1 - hw/adc/Kconfig | 3 - hw/adc/meson.build | 1 - hw/arm/Kconfig | 3 +- hw/block/Kconfig | 3 - hw/block/meson.build | 1 - hw/gpio/Kconfig | 4 - hw/gpio/meson.build | 1 - hw/ide/Kconfig | 6 - hw/ide/meson.build | 1 - hw/meson.build | 1 - hw/misc/Kconfig | 4 +- hw/misc/meson.build | 1 + hw/misc/trace-events | 6 + hw/pcmcia/Kconfig | 2 - hw/pcmcia/meson.build | 1 - hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + hw/ssi/trace-events | 10 + qemu-options.hx | 16 - 81 files changed, 1800 insertions(+), 2048 deletions(-) delete mode 100644 docs/devel/blkdebug.txt rename docs/devel/{lockcnt.txt => lockcnt.rst} (75%) create mode 100644 docs/devel/multiple-iothreads.rst delete mode 100644 docs/devel/multiple-iothreads.txt rename docs/devel/{rcu.txt => rcu.rst} (73%) create mode 100644 docs/devel/testing/blkdebug.rst rename docs/devel/{blkverify.txt => testing/blkverify.rst} (77%) delete mode 100644 include/hw/adc/max111x.h create mode 100644 include/hw/misc/stm32_rcc.h delete mode 100644 include/hw/pcmcia.h create mode 100644 include/hw/ssi/allwinner-a10-spi.h create mode 100644 include/qemu/lockcnt.h create mode 100644 tests/qtest/stm32l4x5.h delete mode 100644 hw/adc/max111x.c delete mode 100644 hw/block/ecc.c delete mode 100644 hw/gpio/max7310.c delete mode 100644 hw/ide/microdrive.c create mode 100644 hw/misc/stm32_rcc.c delete mode 100644 hw/pcmcia/pcmcia.c create mode 100644 hw/ssi/allwinner-a10-spi.c delete mode 100644 hw/pcmcia/Kconfig delete mode 100644 hw/pcmcia/meson.build . Date: Tue, 15 Oct 2024 16:16:46 +0200 From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 00/25] x86 and KVM patches for 2024-10-15 The following changes since commit aa54f5be44be786636a5d51cc1612ad208a24849: tests: update lcitool to fix freebsd py311-yaml rename (2024-10-14 15:54:24 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 4bfdcb24fa5dc0844d0e4ab2cebb6687a233c0ff: target/i386: Use only 16 and 32-bit operands for IN/OUT (2024-10-15 16:15:47 +0200) ---------------------------------------------------------------- * target/i386: Fixes for IN and OUT with REX prefix * target/i386: New CPUID features and logic fixes * target/i386: Add support save/load HWCR MSR * target/i386: Move more instructions to new decoder; separate decoding and IR generation * target/i386/tcg: Use DPL-level accesses for interrupts and call gates * accel/kvm: perform capability checks on VM file descriptor when necessary * accel/kvm: dynamically sized kvm memslots array * target/i386: fixes for Hyper-V * docs/system: Add recommendations to Hyper-V enlightenments doc ---------------------------------------------------------------- Chao Gao (1): target/i386: Add more features enumerated by CPUID.7.2.EDX Gao Shiyuan (1): target/i386: Add support save/load HWCR MSR Paolo Bonzini (9): target/i386: convert bit test instructions to new decoder target/i386: decode address before going back to translate.c target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder target/i386: do not check PREFIX_LOCK in old-style decoder target/i386: list instructions still in translate.c target/i386: assert that cc_op* and pc_save are preserved target/i386/tcg: Use DPL-level accesses for interrupts and call gates accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vm Peter Xu (4): KVM: Dynamic sized kvm memslots array KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used KVM: Rename KVMState->nr_slots to nr_slots_max Richard Henderson (1): target/i386: Use only 16 and 32-bit operands for IN/OUT Tom Dohrmann (1): accel/kvm: check for KVM_CAP_READONLY_MEM on VM Vitaly Kuznetsov (4): target/i386: Fix conditional CONFIG_SYNDBG enablement target/i386: Exclude 'hv-syndbg' from 'hv-passthrough' target/i386: Make sure SynIC state is really updated before KVM_RUN docs/system: Add recommendations to Hyper-V enlightenments doc Xiaoyao Li (4): target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f] target/i386: Enable fdp-excptn-only and zero-fcs-fds target/i386: Construct CPUID 2 as stateful iff times > 1 target/i386: Make invtsc migratable when user sets tsc-khz explicitly docs/system/i386/hyperv.rst | 43 +++- include/sysemu/kvm_int.h | 7 +- target/i386/cpu.h | 9 + target/i386/tcg/decode-new.h | 19 +- accel/kvm/kvm-all.c | 131 ++++++++---- target/i386/cpu.c | 21 +- target/i386/kvm/hyperv.c | 1 + target/i386/kvm/kvm.c | 47 +++-- target/i386/machine.c | 20 ++ target/i386/tcg/seg_helper.c | 17 +- target/i386/tcg/translate.c | 444 ++++++--------------------------------- target/i386/tcg/decode-new.c.inc | 145 +++++++++---- target/i386/tcg/emit.c.inc | 246 +++++++++++++++++++++- accel/kvm/trace-events | 1 + 14 files changed, 666 insertions(+), 485 deletions(-) -- 2.46.2 . Date: Tue, 15 Oct 2024 15:18:04 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL v2 00/28] target-arm queue v2: added missing qtest_quit() call to the new STM32L4x5 qtest, which was causing the test to hang on OpenBSD. -- PMM The following changes since commit 35152940b78e478b97051a799cb6275ced03192e: Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-10-14 17:05:25 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241015-1 for you to fetch changes up to f160a4f8d0ef322377db3519c0aa088ccd99edf1: hw/arm/xilinx_zynq: Add various missing unimplemented devices (2024-10-15 15:16:17 +0100) ---------------------------------------------------------------- target-arm queue: * hw/arm/omap1: Remove unused omap_uwire_attach() method * stm32f405: Add RCC device to stm32f405 SoC * arm/gicv3: add missing casts * hw/misc: Create STM32L4x5 SYSCFG clock * hw/arm: Add SPI to Allwinner A10 * hw/intc/omap_intc: Remove now-unnecessary abstract base class * hw/char/pl011: Use correct masks for IBRD and FBRD * docs/devel: Convert txt files to rST * Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only by now-removed omap/pxa2xx boards) * vl.c: Remove pxa2xx-specific -portrait and -rotate options * dma: Fix function names in documentation * hw/arm/xilinx_zynq: Add various missing unimplemented devices ---------------------------------------------------------------- Akihiko Odaki (1): dma: Fix function names in documentation Alexandra Diupina (3): hw/intc/arm_gicv3: Add cast to match the documentation hw/intc/arm_gicv3: Add cast to match the documentation hw/intc/arm_gicv3_cpuif: Add cast to match the documentation Chao Liu (1): hw/arm/xilinx_zynq: Add various missing unimplemented devices Inès Varhol (3): hw/misc: Create STM32L4x5 SYSCFG clock hw/clock: Expose 'qtest-clock-period' QOM property for QTests tests/qtest: Check STM32L4x5 clock connections Peter Maydell (15): hw/intc/omap_intc: Remove now-unnecessary abstract base class hw/char/pl011: Use correct masks for IBRD and FBRD docs/devel/blkdebug: Convert to rST format docs/devel/blkverify: Convert to rST format docs/devel/lockcnt: Convert to rST format docs/devel/multiple-iothreads: Convert to rST format docs/devel/rcu: Convert to rST format include: Move QemuLockCnt APIs to their own header docs/devel/lockcnt: Include kernel-doc API documentation hw/adc: Remove MAX111X device hw/gpio: Remove MAX7310 device hw/ide: Remove DSCM-1XXXX microdrive device model hw: Remove PCMCIA subsystem hw/block: Remove ecc vl.c: Remove pxa2xx-specific -portrait and -rotate options Philippe Mathieu-Daudé (1): hw/arm/omap1: Remove unused omap_uwire_attach() method Román Cárdenas Rodríguez (2): hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCs hw/arm/stm32f405: Add RCC device to stm32f405 SoC Strahinja Jankovic (2): hw/ssi: Allwinner A10 SPI emulation hw/arm: Add SPI to Allwinner A10 MAINTAINERS | 10 +- docs/about/removed-features.rst | 23 + docs/devel/blkdebug.txt | 162 ------ docs/devel/clocks.rst | 6 + docs/devel/index-api.rst | 1 + docs/devel/index-internals.rst | 2 + docs/devel/{lockcnt.txt => lockcnt.rst} | 89 +-- docs/devel/multiple-iothreads.rst | 139 +++++ docs/devel/multiple-iothreads.txt | 130 ----- docs/devel/{rcu.txt => rcu.rst} | 172 +++--- docs/devel/testing/blkdebug.rst | 177 ++++++ .../devel/{blkverify.txt => testing/blkverify.rst} | 30 +- docs/devel/testing/index.rst | 2 + docs/system/arm/cubieboard.rst | 1 + docs/system/arm/stm32.rst | 3 +- include/block/aio.h | 1 + include/hw/adc/max111x.h | 56 -- include/hw/arm/allwinner-a10.h | 2 + include/hw/arm/omap.h | 10 +- include/hw/arm/stm32f405_soc.h | 2 + include/hw/block/flash.h | 11 - include/hw/core/cpu.h | 1 + include/hw/misc/stm32_rcc.h | 91 +++ include/hw/misc/stm32l4x5_syscfg.h | 1 + include/hw/pcmcia.h | 66 --- include/hw/ssi/allwinner-a10-spi.h | 57 ++ include/qemu/lockcnt.h | 130 +++++ include/qemu/thread.h | 111 ---- include/sysemu/dma.h | 11 +- include/sysemu/sysemu.h | 1 - tests/qtest/stm32l4x5.h | 42 ++ accel/accel-blocker.c | 1 + hw/adc/max111x.c | 236 -------- hw/arm/allwinner-a10.c | 8 + hw/arm/omap1.c | 29 +- hw/arm/stm32f405_soc.c | 12 +- hw/arm/stm32l4x5_soc.c | 2 + hw/arm/xilinx_zynq.c | 70 +++ hw/block/ecc.c | 91 --- hw/char/pl011.c | 4 +- hw/core/clock.c | 16 + hw/core/cpu-common.c | 1 + hw/gpio/max7310.c | 217 ------- hw/ide/microdrive.c | 644 --------------------- hw/intc/arm_gicv3_cpuif.c | 6 +- hw/intc/omap_intc.c | 13 +- hw/misc/stm32_rcc.c | 162 ++++++ hw/misc/stm32l4x5_syscfg.c | 19 +- hw/pcmcia/pcmcia.c | 24 - hw/ssi/allwinner-a10-spi.c | 561 ++++++++++++++++++ system/globals.c | 1 - system/vl.c | 11 - tests/qtest/stm32l4x5_gpio-test.c | 23 + tests/qtest/stm32l4x5_syscfg-test.c | 20 +- tests/qtest/stm32l4x5_usart-test.c | 28 + ui/input.c | 36 -- util/aio-posix.c | 1 + util/aio-win32.c | 1 + util/async.c | 1 + util/fdmon-epoll.c | 1 + util/lockcnt.c | 1 + hw/Kconfig | 1 - hw/adc/Kconfig | 3 - hw/adc/meson.build | 1 - hw/arm/Kconfig | 3 +- hw/block/Kconfig | 3 - hw/block/meson.build | 1 - hw/gpio/Kconfig | 4 - hw/gpio/meson.build | 1 - hw/ide/Kconfig | 6 - hw/ide/meson.build | 1 - hw/meson.build | 1 - hw/misc/Kconfig | 4 +- hw/misc/meson.build | 1 + hw/misc/trace-events | 6 + hw/pcmcia/Kconfig | 2 - hw/pcmcia/meson.build | 1 - hw/ssi/Kconfig | 4 + hw/ssi/meson.build | 1 + hw/ssi/trace-events | 10 + qemu-options.hx | 16 - 81 files changed, 1802 insertions(+), 2048 deletions(-) delete mode 100644 docs/devel/blkdebug.txt rename docs/devel/{lockcnt.txt => lockcnt.rst} (75%) create mode 100644 docs/devel/multiple-iothreads.rst delete mode 100644 docs/devel/multiple-iothreads.txt rename docs/devel/{rcu.txt => rcu.rst} (73%) create mode 100644 docs/devel/testing/blkdebug.rst rename docs/devel/{blkverify.txt => testing/blkverify.rst} (77%) delete mode 100644 include/hw/adc/max111x.h create mode 100644 include/hw/misc/stm32_rcc.h delete mode 100644 include/hw/pcmcia.h create mode 100644 include/hw/ssi/allwinner-a10-spi.h create mode 100644 include/qemu/lockcnt.h create mode 100644 tests/qtest/stm32l4x5.h delete mode 100644 hw/adc/max111x.c delete mode 100644 hw/block/ecc.c delete mode 100644 hw/gpio/max7310.c delete mode 100644 hw/ide/microdrive.c create mode 100644 hw/misc/stm32_rcc.c delete mode 100644 hw/pcmcia/pcmcia.c create mode 100644 hw/ssi/allwinner-a10-spi.c delete mode 100644 hw/pcmcia/Kconfig delete mode 100644 hw/pcmcia/meson.build . Date: Tue, 15 Oct 2024 12:44:09 -0300 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 00/33] Endianness cleanup patches for 2024-10-15 The following changes since commit c155d13167c6ace099e351e28125f9eb3694ae27: Merge tag 'chr-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-10-15 10:30:43 +0100) are available in the Git repository at: https://github.com/philmd/qemu.git tags/single-binary-20241015 for you to fetch changes up to 3e8f019be77d1b648bca0af0121da3bb37766509: hw/mips: Have mips_cpu_create_with_clock() take an endianness argument (2024-10-15 12:21:06 -0300) One checkpatch warning due to wide comment: WARNING: line over 80 characters #108: FILE: hw/i386/multiboot.c:380: + stl_le_p(bootinfo + MBI_BOOT_DEVICE, 0x8000ffff); /* XXX: use the -boot switch? */ ---------------------------------------------------------------- Remove some target-specific endianness knowledge from target/. For MIPS, propagate endianness at the board level, using QOM property. ---------------------------------------------------------------- Philippe Mathieu-Daudé (33): qemu/bswap: Undefine CPU_CONVERT() once done exec/tswap: Massage target_needs_bswap() definition exec/memop: Remove unused memop_big_endian() helper target/hexagon: Replace ldtul_p() -> ldl_p() target/alpha: Replace ldtul_p() -> ldq_p() gdbstub/helpers: Introduce ldtul_$endian_p() helpers target/alpha: Use explicit little-endian LD/ST API target/hexagon: Use explicit little-endian LD/ST API hw/i386: Use explicit little-endian LD/ST API target/avr: Use explicit little-endian LD/ST API linux-user/i386: Use explicit little-endian LD/ST API target/loongarch: Use explicit little-endian LD/ST API target/tricore: Use explicit little-endian LD/ST API target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl() target/ppc: Use tcg_constant_tl() instead of tcg_gen_movi_tl() hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry target/mips: Declare mips_env_is_bigendian() in 'internal.h' target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() target/mips: Introduce mo_endian_env() helper target/mips: Replace MO_TE by mo_endian_env() in get_pte() target/mips: Convert mips16e decr_and_load/store() macros to functions target/mips: Factor mo_endian_rev() out of MXU code target/mips: Explode MO_TExx -> MO_TE | MO_xx target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() target/mips: Remove unused MEMOP_IDX() macro target/mips: Introduce mo_endian() helper target/mips: Replace MO_TE by mo_endian() target/mips: Have gen_addiupc() expand $pc during translation target/mips: Use gen_op_addr_addi() when possible target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() target/mips: Expose MIPSCPU::is_big_endian property hw/mips/cps: Set the vCPU 'cpu-big-endian' property hw/mips: Have mips_cpu_create_with_clock() take an endianness argument include/exec/memop.h | 6 - include/exec/tswap.h | 2 +- include/gdbstub/helpers.h | 4 + include/hw/mips/cps.h | 1 + include/qemu/bswap.h | 2 + target/mips/cpu.h | 7 +- target/mips/internal.h | 10 ++ target/mips/tcg/translate.h | 13 +- hw/i386/multiboot.c | 39 +++-- hw/i386/x86-common.c | 26 +-- hw/mips/cps.c | 4 + hw/mips/fuloong2e.c | 2 +- hw/mips/jazz.c | 3 +- hw/mips/loongson3_virt.c | 2 +- hw/mips/malta.c | 5 +- hw/mips/mipssim.c | 3 +- hw/xtensa/xtfpga.c | 12 +- linux-user/i386/signal.c | 4 +- target/alpha/gdbstub.c | 2 +- target/avr/gdbstub.c | 4 +- target/hexagon/gdbstub.c | 10 +- target/loongarch/gdbstub.c | 8 +- target/mips/cpu.c | 17 +- target/mips/tcg/ldst_helper.c | 15 +- target/mips/tcg/msa_helper.c | 8 - target/mips/tcg/mxu_translate.c | 18 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/mips/tcg/translate.c | 193 ++++++++++------------ target/mips/tcg/tx79_translate.c | 8 +- target/ppc/translate.c | 13 +- target/tricore/gdbstub.c | 2 +- target/tricore/translate.c | 3 +- target/mips/tcg/micromips_translate.c.inc | 34 ++-- target/mips/tcg/mips16e_translate.c.inc | 118 +++++++------ target/mips/tcg/nanomips_translate.c.inc | 162 ++++++++---------- 35 files changed, 370 insertions(+), 392 deletions(-) -- 2.45.2 . Date: Wed, 16 Oct 2024 16:30:58 +0800 From: Song Gao To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PULL 0/5] loongarch-to-apply queue The following changes since commit f774a677507966222624a9b2859f06ede7608100: Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-10-15 15:18:22 +0100) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20241016 for you to fetch changes up to e376c2d87cbbad3483adcd5e827bdd144edb7d2c: hw/loongarch/fw_cfg: Build in common_ss[] (2024-10-16 16:06:07 +0800) ---------------------------------------------------------------- pull-loongarch-20241016 ---------------------------------------------------------------- Bibo Mao (3): acpi: ged: Add macro for acpi sleep control register hw/loongarch/virt: Add FDT table support with acpi ged pm register target/loongarch: Avoid bits shift exceeding width of bool type Philippe Mathieu-Daudé (2): hw/loongarch/virt: Remove unnecessary 'cpu.h' inclusion hw/loongarch/fw_cfg: Build in common_ss[] hw/acpi/generic_event_device.c | 6 +++--- hw/loongarch/meson.build | 2 +- hw/loongarch/virt.c | 39 ++++++++++++++++++++++++++++++++++ include/hw/acpi/generic_event_device.h | 7 ++++-- include/hw/loongarch/virt.h | 1 - target/loongarch/arch_dump.c | 6 +----- 6 files changed, 49 insertions(+), 12 deletions(-) . Date: Thu, 17 Oct 2024 19:44:08 +0200 From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org Subject: [PULL v2 00/26] x86 and KVM patches for 2024-10-15 The following changes since commit f774a677507966222624a9b2859f06ede7608100: Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/p= maydell/qemu-arm into staging (2024-10-15 15:18:22 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 15d955975bd484c2c66af0d6daaa02a7d04d2256: target/i386: Use only 16 and 32-bit operands for IN/OUT (2024-10-17 19:41= :30 +0200) ---------------------------------------------------------------- * tcg/s390x: Fix for TSTEQ/TSTNE * target/i386: Fixes for IN and OUT with REX prefix * target/i386: New CPUID features and logic fixes * target/i386: Add support save/load HWCR MSR * target/i386: Move more instructions to new decoder; separate decoding and IR generation * target/i386/tcg: Use DPL-level accesses for interrupts and call gates * accel/kvm: perform capability checks on VM file descriptor when necessary * accel/kvm: dynamically sized kvm memslots array * target/i386: fixes for Hyper-V * docs/system: Add recommendations to Hyper-V enlightenments doc ---------------------------------------------------------------- v1->v2: new patch to fix tcg/s390x mark new patch and "check for KVM_CAP_READONLY_MEM on VM" for stable Chao Gao (1): target/i386: Add more features enumerated by CPUID.7.2.EDX Gao Shiyuan (1): target/i386: Add support save/load HWCR MSR Paolo Bonzini (10): tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE target/i386: convert bit test instructions to new decoder target/i386: decode address before going back to translate.c target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder target/i386: do not check PREFIX_LOCK in old-style decoder target/i386: list instructions still in translate.c target/i386: assert that cc_op* and pc_save are preserved target/i386/tcg: Use DPL-level accesses for interrupts and call gates accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES on vm Peter Xu (4): KVM: Dynamic sized kvm memslots array KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used KVM: Rename KVMState->nr_slots to nr_slots_max Richard Henderson (1): target/i386: Use only 16 and 32-bit operands for IN/OUT Tom Dohrmann (1): accel/kvm: check for KVM_CAP_READONLY_MEM on VM Vitaly Kuznetsov (4): target/i386: Fix conditional CONFIG_SYNDBG enablement target/i386: Exclude 'hv-syndbg' from 'hv-passthrough' target/i386: Make sure SynIC state is really updated before KVM_RUN docs/system: Add recommendations to Hyper-V enlightenments doc Xiaoyao Li (4): target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f] target/i386: Enable fdp-excptn-only and zero-fcs-fds target/i386: Construct CPUID 2 as stateful iff times > 1 target/i386: Make invtsc migratable when user sets tsc-khz explicitly docs/system/i386/hyperv.rst | 43 +++- include/sysemu/kvm_int.h | 7 +- target/i386/cpu.h | 9 + target/i386/tcg/decode-new.h | 19 +- accel/kvm/kvm-all.c | 131 ++++++++---- target/i386/cpu.c | 21 +- target/i386/kvm/hyperv.c | 1 + target/i386/kvm/kvm.c | 47 +++-- target/i386/machine.c | 20 ++ target/i386/tcg/seg_helper.c | 17 +- target/i386/tcg/translate.c | 444 ++++++-----------------------------= ---- target/i386/tcg/decode-new.c.inc | 145 +++++++++---- target/i386/tcg/emit.c.inc | 246 +++++++++++++++++++++- tcg/s390x/tcg-target.c.inc | 24 ++- accel/kvm/trace-events | 1 + 15 files changed, 682 insertions(+), 493 deletions(-) --=20 2.46.2 From: Paolo Bonzini Date: Thu, 17 Oct 2024 11:09:52 +0200 Subject: [PULL 11/26] tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit 32-bit TSTEQ and TSTNE is subject to the same constraints as for 64-bit, but setcond_i32 and negsetcond_i32 were incorrectly using TCG_CT_CONST ("i") instead of TCG_CT_CONST_CMP ("C"). Adjust the constraint and make tcg_target_const_match use the same sequence as tgen_cmp2: first check if the constant is a valid operand for TSTEQ/TSTNE, then accept everything for 32-bit non-test comparisons, finally check if the constant is a valid operand for 64-bit non-test comparisons. Reported-by: Philippe Mathieu-Daud=C3=A9 Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini --- tcg/s390x/tcg-target.c.inc | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a5d57197a4b..27bccc14e50 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -565,6 +565,20 @@ static bool tcg_target_const_match(int64_t val, int ct, } =20 if (ct & TCG_CT_CONST_CMP) { + if (is_tst_cond(cond)) { + if (is_const_p16(uval) >=3D 0) { + return true; /* TMxx */ + } + if (risbg_mask(uval)) { + return true; /* RISBG */ + } + return false; + } + + if (type =3D=3D TCG_TYPE_I32) { + return true; + } + switch (cond) { case TCG_COND_EQ: case TCG_COND_NE: @@ -584,13 +598,7 @@ static bool tcg_target_const_match(int64_t val, int ct, break; case TCG_COND_TSTNE: case TCG_COND_TSTEQ: - if (is_const_p16(uval) >=3D 0) { - return true; /* TMxx */ - } - if (risbg_mask(uval)) { - return true; /* RISBG */ - } - break; + /* checked above, fallthru */ default: g_assert_not_reached(); } @@ -3231,9 +3239,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: + return C_O1_I2(r, r, ri); case INDEX_op_setcond_i32: case INDEX_op_negsetcond_i32: - return C_O1_I2(r, r, ri); case INDEX_op_setcond_i64: case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rC); --=20 2.46.2 .